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Message
From: Mark McDougall<markm@v...>
Date: Fri Dec 2 09:07:02 CET 2005
Subject: [pci] PCI read burst
TAN Joseph wrote:> I'm using the OpenCores PCI Bridge core to implement a PCI target
> unit and require the target to handle burst reads.
>
> My problem is that every Memory Read command (C/BE# = 0x6) results in
> the PCI bridge issuing a retry. In this case, how is the PCI master
> meant to keep FRAME# asserted over a number of clock cycles to
> indicate a burst read transaction? In the PCI Bridge's Core
> specification page 90 Figure 6.19, the timing diagram shows that
> FRAME# asserted over 5 clock cycles.
All PCI read requests are handled as Delayed READs by the PCI core. This
means that all reads shall be terminated with retry whilst they complete
on the wishbone bus.
Regards,
--
Mark McDougall, Software Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
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