|
Message
From: TAN Joseph<Joseph.TAN@T...>
Date: Fri Dec 2 08:46:04 CET 2005
Subject: [pci] PCI read burst
Hi,I'm using the OpenCores PCI Bridge core to implement a PCI target unit and require the target to handle burst reads. My problem is that every Memory Read command (C/BE# = 0x6) results in the PCI bridge issuing a retry. In this case, how is the PCI master meant to keep FRAME# asserted over a number of clock cycles to indicate a burst read transaction? In the PCI Bridge's Core specification page 90 Figure 6.19, the timing diagram shows that FRAME# asserted over 5 clock cycles. I found the closest thing to a burst read of the target is to issue a Memory Read Multiple (C/BE# = 0xC) or Memory Read Line (C/BE# = 0xE). While this is a workaround, my issue with this is that my current design memory is not considered prefetchable. Cheers,
--
Joseph Tan
Hardware Engineer
--------------------------------------------------
Tenix Defence Pty Ltd
Electronic Systems Division
Second Avenue, Technology Park
Mawson Lakes, South Australia 5095
Email: joseph.tan@t...
Ph +61 08 8300 4418 (Australia)
Fax +61 08 8349 7420
|
Browse
