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From: "Burroughs, Timothy D." <timothy.burroughs@n...>

I do not have a Xilinx PCI dev board, but I have an AvNET PCI dev board.  
The board is similar in functionality.

I can not tell for sure for your Xilinx board, but on the AvNET board, you 
have to change some jumpers to make the PCI interface part of the chain.  
This make the board accessible via JTAG through the JTAG port of the board 
(through the JTAG interface header pins of the board) as default.  Those are 
soldered jumpers (zero-ohm resistors).  I would suspect something similar 
may be present on the Xilinx board.  You should check with the user guide of 
the dev board.

If you can see, from the PC, all the interfaces on your conputer, but not 
the dev board, it is likely that the dev board simply bypass JTAG (send the 
PCI TDI pin directly to PCI TDO pin).  Some soledering could do the trick.

Eric

>From: "Burroughs, Timothy D." <timothy.burroughs@n...>
>Reply-To: "Discussion list about free,  open source PCI IP core" 
><pci@o...>
>To: "Discussion list about free, open source PCI IP core" 
><pci@o...>
>Subject: RE: [pci] GPIO Core
>Date: Wed, 17 Aug 2005 11:48:05 -0500
>
>Does anyone have any experience using JTAG interface on the Xilinx Spartan 
>-3 Starter kit?
>I am having trouble with the JTAG communication between my laptop and the 
>proto-type
>card? It can't see the FPGA or serial PROM
>
>Will appreciate any advice
>thx
>
>Tim Burroughs
>mailto:tburroughs@n...
>
>
>-----Original Message-----
>From: pci-bounces@o... [mailto:pci-bounces@o...]On
>Behalf Of Mark McDougall
>Sent: Tuesday, August 16, 2005 8:16 PM
>To: Discussion list about free, open source PCI IP core
>Subject: Re: [pci] GPIO Core
>
>
>jtrabal@e... wrote:
>
> > My questions are:
> >
> > 1) How can I program the corresponding bit in the control register to
> > 'output mode' ('1')?
> >
> > 2) How can I program the GPIO pin's output level by writing to the
> > corresponding bit in the Line Register?
>
>(Verilog code snipped)
>
>No! The idea is to program the I/O pin from the host software! Once
>everything has been hooked up to the wishbone bus, you configure the
>image in the FPGA and then you can write to the registers using software
>on the host (PC?) to talk via the BAR memory / I/O space. This is how
>you select the input or output mode of each pin.
>
>Regards,
>
>--
>Mark McDougall, Software Engineer
>Virtual Logic Pty Ltd, <http://www.vl.com.au>
>21-25 King St, Rockdale, 2216
>Ph: +612-9599-3255 Fax: +612-9599-3266
>
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