OPENCORES.ORG

Hi!

Hi Miha Dolenc 
That really helped me building up my confidance.

Thanks alot for your help

Regards
Rajan Gajjar

--- Miha Dolenc <mihad@o...> wrote:

> Hi!
> 
> You are right about the RAMs.
> Make sure you define PCI_RAM_DONT_SHARE and
> WB_RAM_DONT_SHARE also.
> About removing the WB Slave Unit:
> You can remove it completely, but you have to be
> carefull
> how you wire its outputs.
> If you hardwire the wrong value, the code will be
> broken.
> I suggest that you run a simulation only to apply
> reset to the core.
> The values on the WB slave unit's outputs during
> reset are the ones you 
> should put on the wires
> after the unit is removed.
> 
> Hope this helps,
> 
> regards
> Miha Dolenc
> 
> ----- Original Message ----- 
> From: <rajan_dd@y...>
> To: <pci@o...>
> Sent: Sunday, September 11, 2005 11:48 AM
> Subject: [pci] Implement fpga specific Ram model on
> MAX II
> 
> 
> > Dear sir
> >
> > About removing the save module, I have very less
> logic area available
> > and I have found removing the slave module frees
> more space the just
> > grounding, so I would like to remove the slave
> module and other
> > modules if they can be and if they will not have
> any adverse effect on
> > the core. Please let me know if it is possible to
> reduce the logis
> > used in any other way.
> >
> > As someone from the forum said to implement fpga
> specific ram model, I
> > tried to do it. But I found out that MAX II (CPLD
> im using) dose not
> > have any kind of RAM blocks. So the ram has to be
> implemented in the
> > logic area itself.
> > And a Generic two-port synchronous RAM model is
> provided in both the
> > files i.e. pci_pci_tpram.v, pci_wb_tpram.v.
> >
> > The code of generic ram is as bellow:
> >
> > `ifdef PCI_WB_RAM_SELECTED // if this is defined
> it dose not implement
> > the generic ram
> > `else
> >    //
> >    // Generic two-port synchronous RAM model
> >    //
> >
> >    //
> >    // Generic RAM's registers and wires
> >    //
> >    reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
> >    reg [dw-1:0] do_reg_b; // RAM data output
> register
> >
> >    //
> >    // Data output drivers
> >    //
> >    assign do_a = {dw{1'b0}}    ;
> >    assign do_b = do_reg_b      ;
> >
> >    //
> >    // RAM read and write
> >    //
> >    always @(posedge clk_a)
> >    if (ce_a && we_a)
> >    mem[addr_a] <= #1 di_a;
> >
> >    //
> >    // RAM read and write
> >    //
> >    always @(posedge clk_b)
> >    if (ce_b)
> >    do_reg_b <= #1 mem[addr_b];
> > `endif
> >
> > So if  PCI_WB_RAM_SELECTED is not defined the
> generic ram is used, and
> > in my case I think because MAX II dose not have
> any ram blocks I don't
> > need to implement any specific ram, and let the
> compiler use the
> > generic ram.
> >
> > This is what I have learned after following some
> instructions on
> > theforoum, please let me know if im wrong
> anywhere.
> >
> > Please note MAX II dose not have any kind of RAM
> block
> >
> > Im using Quartus II Ver. 5 for this project with
> MAX II family of CLPD.
> >
> > Thankyou in advance.
> >
> > Regards
> > Rajan
> > _______________________________________________
> > http://www.opencores.org/mailman/listinfo/pci 
> 
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/pci
> 

______________________________________________________ 
Yahoo! for Good 
Donate to the Hurricane Katrina relief effort. 
http://store.yahoo.com/redcross-donate3/ 