|
Message
From: Burroughs, Timothy D.<timothy.burroughs@n...>
Date: Wed Aug 17 18:47:07 CEST 2005
Subject: [pci] GPIO Core
Does anyone have any experience using JTAG interface on the Xilinx Spartan -3 Starter kit?
I am having trouble with the JTAG communication between my laptop and the proto-type
card? It can't see the FPGA or serial PROM
Will appreciate any advice
thx
Tim Burroughs
mailto:tburroughs@n...
-----Original Message-----
From: pci-bounces@o... [mailto:pci-bounces@o...]On
Behalf Of Mark McDougall
Sent: Tuesday, August 16, 2005 8:16 PM
To: Discussion list about free, open source PCI IP core
Subject: Re: [pci] GPIO Core
jtrabal@e... wrote:
> My questions are:
>
> 1) How can I program the corresponding bit in the control register to
> 'output mode' ('1')?
>
> 2) How can I program the GPIO pin's output level by writing to the
> corresponding bit in the Line Register?
(Verilog code snipped)
No! The idea is to program the I/O pin from the host software! Once
everything has been hooked up to the wishbone bus, you configure the
image in the FPGA and then you can write to the registers using software
on the host (PC?) to talk via the BAR memory / I/O space. This is how
you select the input or output mode of each pin.
Regards,
--
Mark McDougall, Software Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
_______________________________________________
http://www.opencores.org/mailman/listinfo/pci
|
 |
Browse
