LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Sponsors
  • Mirrors
  • Logos
  • Contact us
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Navigation: All forums > Pci > Message List > Message Post

    Message

    Reply | Reply all
    Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

    From: Mark McDougall<markm@v...>
    Date: Wed Aug 17 03:15:49 CEST 2005
    Subject: [pci] GPIO Core
    Top
    jtrabal@e... wrote:

    > My questions are:
    >
    > 1) How can I program the corresponding bit in the control register to
    > 'output mode' ('1')?
    >
    > 2) How can I program the GPIO pin's output level by writing to the
    > corresponding bit in the Line Register?

    (Verilog code snipped)

    No! The idea is to program the I/O pin from the host software! Once
    everything has been hooked up to the wishbone bus, you configure the
    image in the FPGA and then you can write to the registers using software
    on the host (PC?) to talk via the BAR memory / I/O space. This is how
    you select the input or output mode of each pin.

    Regards,

    --
    Mark McDougall, Software Engineer
    Virtual Logic Pty Ltd, <http://www.vl.com.au>
    21-25 King St, Rockdale, 2216
    Ph: +612-9599-3255 Fax: +612-9599-3266

    ReferenceAuthor
    [pci] GPIO CoreJtrabal

     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.