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Message
From: Jeff Carr<jcarr@l...>
Date: Fri Aug 12 08:41:49 CEST 2005
Subject: [pci] Some Warnings
On 08/11/2005 12:10 PM, jtrabal@e... wrote:
> Hi,
>
> Sorry for bother you again. I am trying to implement the PCI Core with
> the simple_gpio core, which can be found in the following address:
>
> http://www.opencores.com/projects.cgi/web/simple_gpio/overview
>
> I LOC the GPIO I/O pins (which are inout signals) to the FPGA pins using
> the following;
>
> NET "GPIO[1]" LOC = "V12" ;
>
> But when I synthesize, the following warnings occur:
Out of curiousity, what software are you using? The Xilinx ISE or Webpack?
Jeff
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