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From: jtrabal at engin.umass.edu<jtrabal@e...>
Date: Thu Aug 11 21:10:50 CEST 2005
Subject: [pci] Some Warnings
Hi,

Sorry for bother you again. I am trying to implement the PCI Core with
the simple_gpio core, which can be found in the following address:

http://www.opencores.com/projects.cgi/web/simple_gpio/overview

I LOC the GPIO I/O pins (which are inout signals) to the FPGA pins using
the following;

NET "GPIO[1]" LOC = "V12" ;

But when I synthesize, the following warnings occur:

WARNING:NgdBuild:470 - bidirect pad net 'GPIO<1>' has no legal driver

and

WARNING:Par:276 - The signal GPIO<1>_IBUF has no load

Any help with those warnings? I have to define anything more
than "inout [8:1] GPIO" right? Where in the master Wishbone I have to
connect the 8 GPIO pins? Thanks

Regards,
Jorge

Follow up	Author
[pci] Some Warnings	Jeff Carr