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From: jtrabal at engin.umass.edu<jtrabal@e...>
Date: Thu Aug 11 16:49:29 CEST 2005
Subject: [pci] PCI Constraints

Hi,

I am trying to use the PCI Core with the simple_gpio Wishbone core in the Spartan-II 2s200 PCi Board. Right now the design is synthesizing, but looking at the report, 13 timing constraints are not met. The constraint table is resume next: Asterisk (*) preceding a constraint indicates it was not met. This may be due to a setup or hold violation. --------------------------------------------------------------------- ----------- Constraint | Requested | Actual | Logic | | | Levels --------------------------------------------------------------------- ----------- TS_CLK = PERIOD TIMEGRP "CLK" 30 ns HIGH | 30.000ns | 19.125ns | 5 50% | | | --------------------------------------------------------------------- ----------- * COMP "STOP" OFFSET = IN 7 ns BEFORE COMP | 7.000ns | 8.665ns | 4 "CLK" | | | --------------------------------------------------------------------- ----------- * COMP "STOP" OFFSET = OUT 11 ns AFTER COMP | 11.000ns | 13.317ns | 1 "CLK" | | | --------------------------------------------------------------------- ----------- COMP "DEVSEL" OFFSET = IN 7 ns BEFORE COM | 7.000ns | 6.162ns | 4 P "CLK" | | | --------------------------------------------------------------------- ----------- * COMP "DEVSEL" OFFSET = OUT 11 ns AFTER CO | 11.000ns | 13.171ns | 1 MP "CLK" | | | --------------------------------------------------------------------- ----------- * COMP "IRDY" OFFSET = IN 7 ns BEFORE COMP | 7.000ns | 8.468ns | 5 "CLK" | | | --------------------------------------------------------------------- ----------- * COMP "IRDY" OFFSET = OUT 11 ns AFTER COMP | 11.000ns | 12.165ns | 1 "CLK" | | | --------------------------------------------------------------------- ----------- * COMP "TRDY" OFFSET = IN 7 ns BEFORE COMP | 7.000ns | 7.810ns | 4 "CLK" | | | --------------------------------------------------------------------- ----------- * COMP "TRDY" OFFSET = OUT 11 ns AFTER COMP | 11.000ns | 12.865ns | 1 "CLK" | | | --------------------------------------------------------------------- ----------- COMP "PERR" OFFSET = IN 7 ns BEFORE COMP | 7.000ns | 2.112ns | 3 "CLK" | | | --------------------------------------------------------------------- ----------- * COMP "PERR" OFFSET = OUT 11 ns AFTER COMP | 11.000ns | 12.400ns | 1 "CLK" | | | --------------------------------------------------------------------- ----------- COMP "PAR" OFFSET = IN 7 ns BEFORE COMP " | 7.000ns | 4.844ns | 2 CLK" | | | --------------------------------------------------------------------- ----------- * COMP "PAR" OFFSET = OUT 11 ns AFTER COMP | 11.000ns | 13.182ns | 1 "CLK" | | | --------------------------------------------------------------------- ----------- * COMP "FRAME" OFFSET = IN 7 ns BEFORE COMP | 7.000ns | 7.304ns | 5 "CLK" | | | --------------------------------------------------------------------- ----------- * COMP "FRAME" OFFSET = OUT 11 ns AFTER COM | 11.000ns | 13.292ns | 1 P "CLK" | | | --------------------------------------------------------------------- ----------- COMP "SERR" OFFSET = OUT 11 ns AFTER COMP | 11.000ns | 9.788ns | 0 "CLK" | | | --------------------------------------------------------------------- ----------- COMP "REQ" OFFSET = OUT 12 ns AFTER COMP | 12.000ns | 9.790ns | 0 "CLK" | | | --------------------------------------------------------------------- ----------- COMP "IDSEL" OFFSET = IN 7 ns BEFORE COMP | 7.000ns | 3.000ns | 1 "CLK" | | | --------------------------------------------------------------------- ----------- COMP "GNT" OFFSET = IN 10 ns BEFORE COMP | 10.000ns | 9.778ns | 4 "CLK" | | | --------------------------------------------------------------------- ----------- TIMEGRP "PCI_AD" OFFSET = IN 7 ns BEFORE | 7.000ns | 2.293ns | 2 COMP "CLK" | | | --------------------------------------------------------------------- ----------- * TIMEGRP "PCI_AD" OFFSET = OUT 11 ns AFTER | 11.000ns | 14.076ns | 1 COMP "CLK" | | | --------------------------------------------------------------------- ----------- TIMEGRP "PCI_CBE" OFFSET = IN 7 ns BEFORE | 7.000ns | 6.917ns | 4 COMP "CLK" | | | --------------------------------------------------------------------- ----------- * TIMEGRP "PCI_CBE" OFFSET = OUT 11 ns AFTE | 11.000ns | 13.726ns | 1 R COMP "CLK" | | | --------------------------------------------------------------------- ----------- Is that something to worry about? Any suggestion to fix it? Thanks for your help. Regards, Jorge

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[pci] PCI Constraints Gvozden Marinkovic