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Message
From: Nicholas DiMonte<npd@a...>
Date: Mon Aug 8 14:27:41 CEST 2005
Subject: [pci] Question about BARs
Thanks for the reply. I was use to the Altera PCI core which provided
status bits indicating which BAR was being hit, so I was looking for
something simple as that. But that Altera core was never designed to act
like a bridge. So the translation registers makes sense now.
Thanks again,
Nick
Mark McDougall wrote:
> npd@a... wrote:
>
>> I have a question on how one determines on the Wishbone side which BAR
>> that the PCI side is trying to access? Since the BARs are configured
>> by the BIOS on power-up, the Wishbone side would not know which PCI
>> BAR is linked to the predefined memory/io space on the Wishbone side.
>> So how is this done? Would this be a good example of using the
>> Translation Address Reg?
>
>
> Yes, the translation address register determines what address appears
> on the wishbone bus when each of the BARs (memory or I/O images) are
> accessed. On the wishbone side you have no knowledge at all of the PCI
> address that generated the wishbone cycle, nor (directly) which BAR
> was accessed. Everything is keyed off the wishbone address.
>
> Note that these translation address values can be hard-coded in
> pci_user_constants.v so you don't have to worry about having software
> set them up for you.
>
> And, at the risk of confusing matters, you have the same concept going
> back the other way when you're mastering from the wishbone bus -
> another set of BARs and translation addresses.
>
> Regards,
>
--
------------------------------------------------------------------------
Nicholas P. DiMonte
Engineering Specialist
Advance Photon Source, ASD
Argonne National Laboratory
(630) 252-8856 npd@a...
www.aps.anl.gov
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