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Message
From: Mark McDougall<markm@v...>
Date: Sat Aug 6 07:24:17 CEST 2005
Subject: [pci] Question about BARs
npd@a... wrote:> I have a question on how one determines on the Wishbone side which BAR
> that the PCI side is trying to access? Since the BARs are configured
> by the BIOS on power-up, the Wishbone side would not know which PCI
> BAR is linked to the predefined memory/io space on the Wishbone side.
> So how is this done? Would this be a good example of using the
> Translation Address Reg?
Yes, the translation address register determines what address appears on
the wishbone bus when each of the BARs (memory or I/O images) are
accessed. On the wishbone side you have no knowledge at all of the PCI
address that generated the wishbone cycle, nor (directly) which BAR was
accessed. Everything is keyed off the wishbone address.
Note that these translation address values can be hard-coded in
pci_user_constants.v so you don't have to worry about having software
set them up for you.
And, at the risk of confusing matters, you have the same concept going
back the other way when you're mastering from the wishbone bus - another
set of BARs and translation addresses.
Regards,
--
Mark McDougall, Software Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
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