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Message
From: jtrabal at engin.umass.edu<jtrabal@e...>
Date: Wed Aug 3 23:24:18 CEST 2005
Subject: [pci] Wishbone Application
Hi,
Sorry for bother. I am trying to implement the PCI core on a
Spartan II 2s200 PCI Board from Memec. In my design I eliminated
everything related to the wishbone side from the top.v module and
loaded the FPGA. The computer recognized the pci bridge with the lspci
command . Now I am trying to implement the Simple General Purpose
IO core, which is very simple and compatible with Wishbone and you
can download it from here:
http://www.opencores.com/cvsweb.shtml/simple_gpio/rtl/
I am trying to learn how Wishbone works. My questions are: Is this
simple_gpio.v file a top file? or I should include its code in my top.v
code which also have the PCI IOB definitions?
I should LOC the simple_gpio defined wishbone pins?
I am confused with the Wishbone part. Thanks for your help.
Regards,
Jorge
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