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Message
From: Nicholas DiMonte<npd@a...>
Date: Mon Aug 1 15:20:52 CEST 2005
Subject: [pci] how the pci slot going to detect the pci card???
I never suggested that PCI mastering had anything to do with who
configures the core. I will try to be a little more clearer as to what I
experienced.
By not grounding the WB slave unit of the core for target-only
applications, the WB slave unit was trying to execute a PCI cycle when a
PCI host was trying to read and configure the WB PCI side. The PCI host
was never able to read the PCI configuration registers, much less
configure them, due to the core wanting to do its own PCI master cycle.
I had no clue why the BIOS would not configure the PCI core until I
turned on the internal logic analyzer of the FPGA and started to trace
the internal signals of the core. I discovered that the PCI target-unit
would acknowledge configuration commands from the host, but since the
core wanted to do its own PCI cycle at the same time, the core would not
pass any configuration data back to the host. Hence, the PCI host was
never able to configure the core. All because the core was trying to
execute its own PCI master cycle. By grounding the WB slave input
control signals, the internal contention in the core was removed and the
PCI host was able to configure the core.
I hope this helps all that try to use this core as a target-only core.
Nick
Mark McDougall wrote:
> Nicholas DiMonte wrote:
>
>> If you don't disable the PCI master, then it will not allow the Host
>> on the PCI bus to configure the PCI side of the GUEST bridge. With my
>> Altera application this was simply done by grounding some wishbone
>> slave input signals that initiate a PCI master cycle. Just leaving
>> them float caused me trouble in Altera.
>
>
> PCI mastering has absolutely nothing to do with who configures the
> core. If the core is built as a GUEST bridge, then the configuration
> of the core is done by another entity on the PCI bus.
>
> PCI mastering is the ability to *initiate* a transaction on the PCI bus.
>
>> I'm sorry if I gave the impression that the core had to be modified
>> to accomplished this. I myself have been struggling with my Altera
>> application trying to get the FIFO's to work when I discovered the
>> problem above for my target-only device. The fix above allowed the
>> BIOS to configure the PCI configuration registers. Now I have a
>> properly configured core with two BAR's being defined. My only
>> problem seems to be with the Altera RAM's not being configured
>> correctly. Once this is solved I will be a happy camper.
>
>
> Perhaps with 'floating' inputs to the PCI master unit, it was
> preventing the PC host from grabbing the bus to initiate config cycles
> for the core?
>
>> What is a CDBG?
>
>
> <http://www.probo.com/cdbg.htm>
>
> Invaluable for bringing up and debugging PCI designs.
>
> Regards,
>
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