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Message
From: Mark McDougall<markm@v...>
Date: Mon Aug 1 03:01:47 CEST 2005
Subject: [pci] how the pci slot going to detect the pci card???
Nicholas DiMonte wrote:> If you don't disable the PCI master, then it will not allow the Host
> on the PCI bus to configure the PCI side of the GUEST bridge. With my
> Altera application this was simply done by grounding some wishbone
> slave input signals that initiate a PCI master cycle. Just leaving
> them float caused me trouble in Altera.
PCI mastering has absolutely nothing to do with who configures the core.
If the core is built as a GUEST bridge, then the configuration of the
core is done by another entity on the PCI bus.
PCI mastering is the ability to *initiate* a transaction on the PCI bus.
> I'm sorry if I gave the impression that the core had to be modified
> to accomplished this. I myself have been struggling with my Altera
> application trying to get the FIFO's to work when I discovered the
> problem above for my target-only device. The fix above allowed the
> BIOS to configure the PCI configuration registers. Now I have a
> properly configured core with two BAR's being defined. My only
> problem seems to be with the Altera RAM's not being configured
> correctly. Once this is solved I will be a happy camper.
Perhaps with 'floating' inputs to the PCI master unit, it was preventing
the PC host from grabbing the bus to initiate config cycles for the core?
> What is a CDBG?
<http://www.probo.com/cdbg.htm>
Invaluable for bringing up and debugging PCI designs.
Regards,
--
Mark McDougall, Software Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
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