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    Navigation: All forums > Pci > Message List > Message Post

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    From: Nicholas DiMonte<npd@a...>
    Date: Sat Jul 30 15:36:25 CEST 2005
    Subject: [pci] how the pci slot going to detect the pci card???
    Top
    I am by no means a PCI expert, but would like to share my learning
    experience trying to create a PCI target-only device using this core in
    a Altera FPGA.

    If you don't disable the PCI master, then it will not allow the Host on
    the PCI bus to configure the PCI side of the GUEST bridge. With my
    Altera application this was simply done by grounding some wishbone slave
    input signals that initiate a PCI master cycle. Just leaving them float
    caused me trouble in Altera.

    I'm sorry if I gave the impression that the core had to be modified to
    accomplished this. I myself have been struggling with my Altera
    application trying to get the FIFO's to work when I discovered the
    problem above for my target-only device. The fix above allowed the BIOS
    to configure the PCI configuration registers. Now I have a properly
    configured core with two BAR's being defined. My only problem seems to
    be with the Altera RAM's not being configured correctly. Once this is
    solved I will be a happy camper.

    What is a CDBG?

    Nick



    Mark McDougall wrote:

    > Nicholas DiMonte wrote:
    >
    >> This PCI core from Opencores should work as a simple PCI target if
    >> you set it up correctly, but it will require a little more work to
    >> disable the PCI master controller in this core to accomplish this. I
    >> have not done this myself, so I can't show you exactly how to do it
    >> at the moment. Maybe someone on this forum may confirm or deny this
    >> statement, that is, that this core can be used as a PCI target only
    >> core.
    >
    >
    > Why would you need to disable the master unit??? If there's nothing
    > driving the master unit, then it won't interfere at all.
    >
    > If you configure the core in GUEST mode, define the device/vendor ID
    > and the required memory or I/O spaces, it will simply appear on the
    > bus, configured by the PC's BIOS. I'd suggest using something like
    > CDBG to communicate with the target in the early stages.
    >
    > If it hasn't already got one, you'd need to provide a wishbone
    > interface to the 8255 (I'm not clear whether this is a 'real world' IC
    > you intend using or a soft-core version). In any case, there's not a
    > lot of work to do here.
    >
    > As someone suggested, download the PCI and WISHBONE specs.
    >
    > Regards,
    >

     
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