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Hi Jorge,

Hi,
When I synthesize I am getting this warning:
Number of bonded IOBs:                365  out of    288   126% (*) 
Does anyone know why?
Regards,
Jorge
----- Original Message ----- 
From: TAN Joseph<Joseph.TAN@T...> 
To: 
Date: Fri Jul 15 04:25:22 CEST 2005 
Subject: [pci] PCI Bridge Error 

> Hi Jorge, 
> 
> To get started the register transfer level (RTL) code is located in 
> \pci\rtl\verilog. The top level is "pci_bridge32.v". 
> The PDF documentation describes the core in a lot of detail. 
> Essentially 
> you'll have to decide what your PCI device is going to do, 
> appropriately 
> configure the PCI bridge's constants, and then design your WishBone 
> peripheral to talk to the PCI core. 
> In \pci\sw\configurator there is a configurator utility to help you 
> get 
> started with setting the PCI bridge's constants. This utility is 
> very 
> buggy so don't trust its output. However, it can help new users 
> understand what all those 'defines do. Consult the specification 
> and 
> Design Documentation for more detailed information. 
> Cheers, 
> Joseph Tan 
> -----Original Message----- 
> From: pci-bounces at opencores.org [mailto:pci-bounces at 
> opencores.org]On 
> Behalf Of jtrabal at engin.umass.edu 
> Sent: Friday, 15 July 2005 3:41 AM 
> To: alvin.h.tran at gmail.com; pci at opencores.org 
> Subject: Re: [pci] PCI Bridge Error 
> Hi, 
> Thanks for your reply. How can I use the configuration utility for 
> the 
> PCi Bridge? I am trying to open that in Windows XP, but I can't. 
> Thank 
> you for the help. 
> Jorge Trabal 
> ----- Original Message ----- 
> From: alvin tran<alvin.h.tran at g...> 
> To: 
> Date: Wed Jul 13 21:35:43 CEST 2005 
> Subject: [pci] PCI Bridge Error 
> > you have to use the software provided by opencore to generate 
> the 
> > configuration file. 
> > --Alvin 
> > On 7/13/05, jtrabal at engin.umass.edu <jtrabal at 
> > engin.umass.edu> wrote: 
> > > Hi, 
> > > 
> > > I am trying to synthesize the PCI Bridge in webpack 7.1 
> and I 
> > am 
> > > getting the following error: 
> > > 
> > > ERROR:HDLCompilers:26 - "/../Documents and 
> > > 
> > 
> Settings/OpenCores/OpenCores/pci/rtl/verilog/pci_conf_space.v" 
> > line 
> > > 1784 Macro reference `PCI_AT_EN1 is not defined 
> > > ERROR: XST failed 
> > > 
> > > Any help in how to define that? Thanks in advance 
> > > 
> > > Regards, 
> > > Jorge 
> > > _______________________________________________ 
> > > http://www.opencores.org/mailman/listinfo/pci 
> > > 
> > 
> > 
> _______________________________________________ 
> http://www.opencores.org/mailman/listinfo/pci 
> 
>