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Message
From: Mark McDougall<markm@v...>
Date: Fri Jul 15 05:46:21 CEST 2005
Subject: [pci] Re: Pci Digest, Vol 18, Issue 1
Velayutham Venkatachalapathy wrote:> Kindly can some one help in understanding the pci BAR Address
> mechanism.
>
> My ? is: Pls let me know how cpu or host will know that i need 2 mb
> space or 1 mb by reading the Memory or IO bar ...what is the decoding
> mechanism involved.
I'd strongly suggest you read Mindshare's "PCI System Architecture".
The BAR register itself implements only the high-order address bits
above your chosen image size. For example, a 2MB space requires only
address bits 31:21 to be implemented to store a 2MB-aligned base address.
Whatever software is doing the PCI configuration (eg BIOS) will firstly
write "all-1's" to this register and read it back to determine which
bits are implemented - and hence the size of the image. In the example
above, after writing 1's it would read back $FFE00000. The size is
calculated by negating, in this case $200000 = 2MB.
Finally it re-writes the register with the real address it has assigned
to the BAR, which must be "naturally aligned", in this case, aligned on
a 2MB boundary.
So in the opencores PCI core, you use the PCI_AMx define in
pci_user_constants.v to set the mask to, in this case, $FFE0_00 for a
2MB BAR. Similarly, you'd use $FFF0_00 for a 1MB BAR.
Regards,
--
Mark McDougall, Software Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
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