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Message
From: Mark McDougall<markm@v...>
Date: Thu Jul 14 04:29:47 CEST 2005
Subject: [pci] PCI Bridge Error
TAN Joseph wrote:> Well at least the PCI core itself looks OK. I haven't found any
> actual bugs in the Verilog code once I got everything working.
Yeah, that's looking pretty solid this end too. A few problems with the
IDE core mostly, and some struggling with understanding the DMA
pass-thru limitations mainly.
> The actual Verilog source code looks very low-level and not easily
> maintainable. How difficult would it be to extend the design for
> 64-bit PCI and 64-bit WishBone bus?
To be honest, I haven't really looked inside the PCI core, mainly due to
the fact that it appears to work without any problems - and I've had my
fingers very firmly crossed all this time! ;)
Rather, we've spent quite a bit of time trying to turn the PCI testbench
software into something that we can use for arbitrary PCI transactions
in a system testbench - with some limited success. Now *that* is a task
in itself - though to be fair the testbench is really geared towards
doing what it was originally intended - a series of 'pre-canned' tests -
and for that it is remarkably thorough.
Sorry I can't help with the mods.
Regards,
--
Mark McDougall, Software Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
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