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Message
From: Stephen Williams<steve@i...>
Date: Mon Apr 4 17:48:05 CEST 2005
Subject: [pci] PCI Bus at 66 Mhz
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Mihelogiannakis giorgos wrote:
| Hello again!
| I looked into the matter more and have news.
| First of all, i located this post:
| http://www.opencores.org/forums.cgi/cores/2001/11/00057
| In this lists' archives which was a hint into looking more in depth the
| synchronizers, as i have started. The first thing was to study all
| modules which accept signals from both clock domains (wbw_wbr_fifos.v ,
| delayed_sync.v , delayed_write_reg.v and conf_space.v) to see if there
| were any signals that went from one clock domain to another, but not
| through a synchronizer. Fortunately, all such signals either went
| through the synchronizer_flop module, or were driven by the RAM
| instances (which accepted both clocks). The only exception to that is
| delayed_write_reg.v which does not use the synchronizer_flop module but
| uses a flip flop the same way as the _flop module. I didn't see any
| reason why it won't use the _flop module, so i hope i'm not missing
| anything.
Humm, this doesn't appear to be quite adequate. Registers that are
used as synchronizers accross asynchronous clock domains need to
have (in the Xilinx world) the attribute:
~ (* REGISTER_DUPLICATION = "no" *)
I assume other FPGA vedors' tools have a similar attribute. Without this
attribute, the compiler may duplicate the register to try to be helpful
(i.e. for better speed) and those FFs may occasionally get lock onto
different values. Ugh!
It looks like, based on the comments I see in the source, that the various
wide values that are passed are passed as grey codes, so that should
be OK
- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
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