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Message
From: Mihelogiannakis giorgos<mihelog@c...>
Date: Tue Mar 29 19:05:44 CEST 2005
Subject: [pci] PCI Bus at 66 Mhz
Hello everyone,
Sorry to grab your attention for yet another time. The reason this
time is difficulties in making the PCI bus run at 66 Mhz.
According to the timing report while generating a post PNR simulation
model for the PCI bridge, the minimum clock for the PCI bus is 14.2 ns,
which means that 66 Mhz is possible. Therefore, i set the PCI66 constant
which changes a setting in the configuration space (to indicate that it's
capable of 66 Mhz) and makes the testbench produce a PCI llock with 15 ns
period.
Functional simulation works fine, and there is no difference in how the
bridge operates. However, post PNR simulation model is not so cooperative.
Although configuration space accesses have no problem (since they don't
use the PCI bus), when it comes to producing configuration space cycles on
the PCI bus, the PCI bus monitor sees that:
*** monitor - PCI Real OE signals have X's {F, I, D_T_S, AD, CBE, PERR}
'bxx0xx0
which -of course- is what one can see at the waveform. This happens when a
read is requested from address 000001e5 (CNF_DATA register if i am not
mistaken) which would produce a configuration read cycle on the PCI bus.
After that, everything seems damaged in a way, even outputs to the other
side of the bridge are in X state when they were supposed to be at 1.
Continuing with requests (othe requests) does not help.
Post-map simulation model has the same problem, while post-translate
doesn't. If you are using Xilinx ISE as i am, all project properties are
at their default values, while the board is xc2vp70 (family Virtex2P) ,
speed grade -6 and device package ff1517.
Thank you very much in advance for nay help you can provide,
George Michelogiannakis
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