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Good day to everyone,

Hi!
The address conflict occurs every time the FIFO is empty and
something in written into it. This should not cause a problem,
since the data is not used until at least 2 read clock cycles after the
write.
I've once had similar problems with the RAM sim models as you are
describing.
I found out that the models were not working as they should and
when I replaced the models with a different version, everything started
working.
As I can see, your model reports that data on port B is unknown until next
clk B.
That's expected and handled by the core.
The faulty models I've mentioned kept the data in the unknown state
indefenitely.
Can you check if that happens in your case?

Best regards,
Miha Dolenc

----- Original Message ----- 
From: "Mihelogiannakis giorgos" <mihelog@c...>
To: <pci@o...>
Sent: Tuesday, March 15, 2005 10:39 PM
Subject: [pci] FPGA Xilinx RAM Instantiation

> Good day to everyone,
>       I have one quick question regarding instantiating FPGA RAM instances
> to make the PCI bridge fully downloadable to an FPGA. I have defined the
> "XILINX" and "FPGA" constants, which cause pci_wb_tram module to use
> Xilinx's RAMB4_S16_S16 to construct FIFO RAMs. If these two constants are
> not defined, a generic RAM model is used instead, constructed from a
> couple of always@ blocks, and register arrays. The problem i am hacing is
> that when these RAM instances are used, i get many conflict warning
> messages :
>
> # Memory Collision Error on
>
RAMB4_S16_S16:SYSTEM.bridge32_top.bridge.wishbone_slave_unit.fifos.wbr_fifo_
storage.ramb4_s16_s16_1.display_zero
> at simulation time 456465.000 ns
> # A read was performed on address 0a (hex) of Port B while a write was
> requested to the same address on Port A. The write will be successful
> however the read value on Port B is unknown until the next CLKB cycle.
>
> Which refer to an address conflict on the RAM's two ports. As wired in
> pci_wbw_wbr_fifos.v, the read port of each RAM is always set to read (chip

> select and output enable are hardwired to 1) which would surely cause a
> problem at some point of the bridge's peration. The problem is that i have
> tried changing the hardwiring from 1 to a condition whichcould guarantee
> that  each instance is not written  and read at the same time, but every
> change i've made either makes no difference, or causes the bridge to
> malfunction. This conflict is an address conflict, and occurs when the
> FIFO is empty and thus the two points (read and write) point to the same
> address.
>
> With the conflicts, the functional code still works fine, but the post-PNR
> simulation model does not. The simulation model works fine if the gneric
> RAM instance is used (register arrays), but not if this conflict with
> other RAM instances are present.
>
> Has anyone else encountered this or a similar problem when instantiating
> RAM instances for RAM? I would like to avoid generating a seperate RAM
> instance and therefore i would be most grateful for any help.
>
> Than kyou!
>    George Michelogiannakis
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