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From: Otger Ballester<otger@i...>
Date: Wed Feb 9 12:07:39 CET 2005
Subject: [pci] BAR0 and P_BA0
Hi Miha,
First of all thanks for your time and help. Let me explain my
testbench, maybe you find something wrong:
-Guest only exist, it do nothing (Sometimes I read Configuration
Space reg's from GUEST cpu to check if what Host cpu shows about Guest
is the same). In a next stage of my testbench I'll write to HOST.
-Both HOST and GUEST have a 128 KB memory (one for each) only
available from Avalon Master with Avalon @ 0x0 (2 pci images and 2 WB
images for both HOST and GUEST)
-In Avalon-WB wrapper, Avalon Slaves pass to WB slave only 20 LS
address lines, 12 MS lines are set to 0.
-I've put a Nios II for Host (cpu_HOST) and one for Guest (cpu_GUEST)

cpu_HOST tasks(notation: write_XX(address,offset,data)
read_XX(address,offset)
XX:#of bits to write/read
)
-Set PCI Master operation to HOST ( write_16(0x04,0x0,0x04))
-Scan PCI bus (Clear CNF_ADDR. I do a bucle of 20 repeats which
write to CNF_ADDR and read CNF_DATA (if CNF_DATA content differs from
0xFFFF_FFFF a device is present) increment device field of CNF_ADDR. I
store device field of CNF_ADDR for detected devices) (I've changed
pci_AD line connected to IDSEL to check if it works, and it does)
-Device address requirements(I do next for each detected device,
as I have only one device it does one time only.I've connected
pci_AD[12] to GUEST IDSEL):
clear CNF_ADDR (write_32(0x01E0,0x0,0x0)
write CNF_ADDR (write_32(0x01E0,0x0,0x840) (Device field 0x01,
Offset field 0x10(Guest BAR0))
write CNF_DATA (write_32(0x01E4,0x0,0xFFFFFFFF)
read CNF_DATA (read_32(0x01E4,0x0)) (I get 0x00000000)
write CNF_ADDR (write_32(0x01E0,0x0,0x860) (Device field 0x01,
Offset field 0x10(Guest BAR1))
write CNF_DATA (write_32(0x01E4,0x0,0xFFFFFFFF)
read CNF_DATA (read_32(0x01E4,0x0)) (I get 0x00000000)

Regards,
Otger Ballester

Miha Dolenc wrote:

>OK, thats not it then.
>Can you send me the sequence of operations you perform
>to write/read guest BARs? (write offset data, read offset data, ....).
>Maybe I can determine something.
>I also need to know which PCI AD line you connected to GUEST IDSEL input.
>If this won't help, we'll have to exchange some waveforms ;)
>
>Regards,
>Miha Dolenc
>
>----- Original Message -----
>From: "Otger Ballester" <otger@i...>
>To: "Discussion list about free, open source PCI IP core"
><pci@o...>
>Sent: Wednesday, February 09, 2005 10:14 AM
>Subject: Re: [pci] BAR0 and P_BA0
>
>
>
>
>>Hi!
>>
>>To do my testbench I've done some things:
>> -Have a copy of design files for my Host and a copy for my Guest
>> -Rename all GUEST modules from XXX to XXX_guest
>> -Rename all GUEST files to XXX.v to XXX_guest.v (and change `include
>>... of all files)
>>
>>Simulating with Modelsim I read GUEST class code from GUEST cpu and get
>>0x068000 which stands for Other Bridge device, and HOST class code from
>>HOST cpu getting 0x060000 (Host Bridge), so I think my Testbench works
>>fine in this aspect.
>>
>>Regards,
>>Otger Ballester
>>
>>Miha Dolenc wrote:
>>
>>
>>
>>>Hi!
>>>
>>>As this basic operations work in numerous applications already,
>>>there must be something wrong with the testbench.
>>>I wonder how you compile both pci bridge instances into the same
>>>
>>>
>testbench
>
>
>>>environment with different defines.
>>>Can it be that both of the instances come up as HOST when you start
>>>the simulation (HOST instance overwrites GUEST when compiled)?
>>>That could explain that you cannot write to registers from the PCI Bus.
>>>You can easily determine if the instance is host, if you read the device
>>>class register.
>>>(should be "host bridge" for host and "other bridge" for guest - I don't
>>>remember the numbers from the top of my head - they are in
>>>the PCI spec.).
>>> >>>Regards, >>>Miha Dolenc >>> >>>----- Original Message ----- >>>From: "Otger Ballester" <otger@i...> >>>To: <pci@o...> >>>Sent: Tuesday, February 08, 2005 6:45 PM >>>Subject: [pci] BAR0 and P_BA0 >>> >>> >>> >>> >>> >>> >>>>Hi all, >>>> >>>> In my final career project I'm integrating Opencores PCI IP Core >>>>into an Altera Nios system. To simulate it I've done a testbench with >>>>both a guest and a host with a Nios II for each one and a pci arbiter >>>>(I want to implement a Host, but I need a Guest for testbench >>>>purpouses). At the moment I can access (from Host) Guest Configuration >>>>space with type0 configuration cycles (read and write), and of course I >>>>can access Guest and HOST Configuration Space from themselves. >>>> >>>> I've made a wrapper avalon wishbone so I can instantiate the core with >>>>a Nios II. Now I'm developing boot software for Host bridge. I'm >>>>following instructions of chapter "Initialization for HOST >>>>implementation" (3.1.2, page 12). I've successfully followed the first >>>>two steps but I'm stuck at step 3. I have to determine all connected PCI >>>>device's address space requirements following instructions from PCI >>>>Local bus spec's rev 2.2 (page 204): >>>> -write 0xFFFF_FFFF to GUEST BARx >>>> -read GUEST BARx (I allways get 0x0000_0000) >>>> -clear codification bits (3:0 bits for memory mapping, bits 1:0 for >>>>I/O space) >>>> -invert all 32 bits (logical NOT) >>>> -increment by 1 >>>>As I get 0x0 when I read GUEST BARx, I allways get 0 for address space >>>>requirements. >>>> >>>>My configuration define's for GUEST bus bridge are: >>>>//`define NO_CNF_IMAGE >>>>`define PCI_NUM_OF_DEC_ADDR_LINES 20 >>>>`define PCI_AM0 24'hffff_f0 >>>>`define PCI_AM1 24'hfff0_00 >>>>`define PCI_BA0_MEM_IO 1'b0 >>>>`define PCI_BA1_MEM_IO 1'b0 >>>>`define PCI_TA0 24'h0000_0 >>>>`define PCI_TA1 24'h0000_0 >>>>`define PCI_AT_EN0 1'b0 >>>>`define PCI_AT_EN1 1'b1 >>>>`define ADDR_TRAN_IMPL >>>> >>>>Both Guest and Host WB Master are connected to a 128KB memory, so I need >>>>an address space of 128KB at least. >>>> >>>>Can somebody help me? I don't know what I'm doing wrong. >>>>Thanks in advance >>>>_______________________________________________ >>>>attachment.htm >>>> >>>> >>>> >>>> >>>_______________________________________________ >>>attachment.htm >>> >>> >>> >>> > > >---------------------------------------------------------------------------- >---- > > > > >>_______________________________________________ >>attachment.htm >> >> > >_______________________________________________ >attachment.htm > > -------------- next part -------------- An HTML attachment was scrubbed... URL: attachment.htm