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Message
From: Jiangtao Meng<mengjt@y...>
Date: Mon Mar 15 18:44:36 CET 2004
Subject: [pci] Problem with bandwidth
Hello guys,I have some experiences on the PCI bandwidth. Let me explain my
experience a little longer.
I have designed and implemented a PCI board using Xilinx FPGA. The PCI
core is bought from Xilinx. And the board is bought from Insight. The
PCI core from Xilinx is really simple, actually it just translated the
PCI protocol to some Xilinx defined local bus protocol, although still
really like the PCI interface. The good thing is you don't have to
bouther about the PC boot up sequence and configuration. The bad thing
is actually you need to design everything yourself to implement either
the slave or the master mode of your board.
Yes, PCI 33 has the bandwith up to 33MHz x 4 bytes. But to reach that
speed, you must design your board to be in PCI master mode and could do
burst mode transfer to and from PC main memory via PCI bus. Also, your
driver, no matter Linux driver or Windoz driver, must also be able to
initialize your board's master mode.
My board works in the following flow (writing to PC memory):
1. it first sample data from some data source and save these data into a
FIFO.
2. When the FIFO has reached some threshold, say 3/4 full, it will
request a PCI master write request to PCI arbitor.
3. When he gets the grant from the PCI bus arbitor, it begin to write
data to PC memory in burst mode via PCI bus. At this time, my board is
the PCI master, and the PC memory looks like a PCI slave.
4. When finished the transfer, release the PCI bus.
In your case in which speed is only 300us, I think maybe your board is
not in burst mode. You can use scope or FPGA chipscope (sorry, I don't
what's the Altera's counterpart) to sample the PCI bus to see what is
really happening.
And remember, to be in burst mode, both the driver and PCI board should
be configured properly. If any questions, please feel free to contact
me. My email address is
mengjt@y...
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