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Hi Manoj,

Hi again Manoj,
at the moment I have some trouble in getting the core to run. I seems to 
be an timing issue. Sometimes he isn't recognized, sometimes he is 
recognized but not configured  (because the BAR's are not writeable), 
sometimes some bits are wrong.
What tool do you use and have you set some constraints?
I'm using quartus web edition. I've played around with the 
setup/hold/clock2output times but had no success.

Suggestions are welcome ;-)

Best regards,

Adalbert Mueller

adalbert.mueller wrote:

> Hi Manoj,
>
> I even changed the tpram files and had success in compiling the core 
> together with HPI. But till no, I don't know if it's working. I'm just 
> configuring the BAR's and next step will be to try to communicate.
>
> Bye,
>
> Adalbert
>
>
>
> mv wrote:
>
>> Hello Adalbert,
>>
>> I have successfully ported the code to an Altera
>> Cyclone. The blocks you need to change to go from
>> Xilinx to Altera are the tprams (dual-port rams) used
>> in the FIFOs and any internal block rams. I also added
>> a PLL instance to keep the internal clock locked to
>> the input pciclock.
>>
>> You can use the megafunction generator to generate the
>> dual-port rams and PLL.
>> Good luck.
>>
>> Regards,
>> Manoj
>>
>> =============================
>> Manoj Viswambharan
>> Consulting Hardware Engineer
>> manojv@o...
>> =============================
>>
>>
>>
>> --- adalbert.mueller@w... wrote:
>>  
>>
>>> Hi anyone,
>>>
>>> I try to implement the PCI-core onto a altera 1k100
>>> together with the
>>> HPI interface in order to receive data from a DSP.
>>> Unfortunately I'm not a verilog insider but a
>>> willing student :-)
>>> I just began to read the datasheet for the 1k100 and
>>> some messages
>>> inside this forum.
>>> I have one important questions: Does anyone know, if
>>> it's possible or
>>> has somebody already tried it? (maybe with success?)
>>>
>>> I've seen, inside the code are some specific parts
>>> for a Xilinx fpga
>>> which probably have to be changed to the altera
>>> fbga.
>>>
>>> I'm grateful for every hint and informations about
>>> this case.
>>>
>>> Thank's in advance,
>>>
>>> Adalbert Mueller
>>> -- 
>>> To unsubscribe from pci mailing list please visit
>>>   
>>
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>>
>>
>>
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>
>
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