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Hi Manoj,

Hello Adalbert,
Does the post-place-and-route simulation pass? If it
doesn't, than bench testing won't help. As you know
it's easier to debug in the simulator. Get this to
pass first before going to the bench. Also perform
timing simulation after this step. It will be S-L-O-W
but run it as long as you can. It does help shake out
some hard to find bugs. 

The best way to debug the FPGA on the bench (IMHO) is
the SignalTap logic analyzer megacore (or Xilinx
Chipscope for Xilinx FPGAs). If you have room in the
FPGA, you can instantiate this core along with the
rest of your logic. The QuartusII GUI has a decent way
of capturing and displaying the events on screen. The
GUI uses the JTAG interface to communicate with the
FPGA. There are are lots of articles and Appnotes on
Altera's website Re: SignalTap. 

Aside: I'm not an advocate of any FPGA vendor, I just
happened to use Altera for this project. I've used
Xilinx, Actel, & Lattice on other projects. Any of
which will do the job.

I used the logic analyzer core to view the Wishbone
bus. It's a very useful tool for debugging internal
FPGA signals. When prototyping with the FPGA make sure
to pick a larger FPGA than required for the logic. The
SignalTap core uses a lot of block rams depending on
your capture depth. Instantiate the core and check the
resource utilization before committing to the board
design.

If you don't have room for the logic analyzer core,
then try buffering and bringing out the signals of
interest to unused pins on the FPGA. You can hook up
an external logic analyzer to these pins to view the
signals. It helps if you had some spare pins going to
a test connector. SignalTap has a mode that can do
this for you. 

I also used a PCI Analyzer/Exerciser to view the PCI
bus signals and generate bus cycles. You can rent one
for about a $1500/month if needed. 

Good Luck.

Regards,
Manoj

=======================================
Manoj Viswambharan
Consulting Hardware Engineer
manojv@N...
Remove NOSPAM for actual email address.
=======================================

--- "adalbert.mueller" <adalbert.mueller@w...>
wrote:
> Hi Manoj,
> 
> I even changed the tpram files and had success in
> compiling the core 
> together with HPI. But till no, I don't know if it's
> working. I'm just 
> configuring the BAR's and next step will be to try
> to communicate.
> 
> Bye,
> 
> Adalbert
> 
> 
> 
> mv wrote:
> 
> >Hello Adalbert,
> >
> >I have successfully ported the code to an Altera
> >Cyclone. The blocks you need to change to go from
> >Xilinx to Altera are the tprams (dual-port rams)
> used
> >in the FIFOs and any internal block rams. I also
> added
> >a PLL instance to keep the internal clock locked to
> >the input pciclock.
> >
> >You can use the megafunction generator to generate
> the
> >dual-port rams and PLL. 
> >
> >Good luck.
> >
> >Regards,
> >Manoj
> >
> >=============================
> >Manoj Viswambharan
> >Consulting Hardware Engineer
> >manojv@o...
> >=============================
> >
> >
> >
> >--- adalbert.mueller@w... wrote:
> >  
> >
> >>Hi anyone,
> >>
> >>I try to implement the PCI-core onto a altera
> 1k100
> >>together with the
> >>HPI interface in order to receive data from a DSP.
> 
> >>
> >>Unfortunately I'm not a verilog insider but a
> >>willing student :-)
> >>I just began to read the datasheet for the 1k100
> and
> >>some messages
> >>inside this forum. 
> >>
> >>I have one important questions: Does anyone know,
> if
> >>it's possible or
> >>has somebody already tried it? (maybe with
> success?)
> >>
> >>I've seen, inside the code are some specific parts
> >>for a Xilinx fpga
> >>which probably have to be changed to the altera
> >>fbga.
> >>
> >>I'm grateful for every hint and informations about
> >>this case.
> >>
> >>Thank's in advance,
> >>
> >>Adalbert Mueller
> >>--
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> >>    
> >>
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> >
> >
> >
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> 
> 
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