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From: yakgna narayanan <yakgnaa@y...>
Date: Wed, 30 Jul 2003 12:46:21 +0100 (BST)
Subject: [pci] PCI Operational registers (Two clock domain)

hi,
I am having one technical doubt, To whom shall i post
my question.
My doubt is : 
how to handle register for multi clock domains ?
say for e.g a operational register in pci
rega      - 8 bit register
write clk - pci_clk
read clk  - bk_end_clk
For data transfer means we can go for Asynchronous
fifo, whereas for registers, individual bit setting
and clearing is done in different clocks, so we cant
go for RAM's also. So please guide me how to do
verilog code for registers in multi clock domains.

Thanks in Advance,
Regards,
Yakgna

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