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Message
From: liei@v...
Date: Mon, 7 Jul 2003 07:51:10 -0100
Subject: Re: [pci] PCI target
I cannot figure out that which kind of memory do you prefer to
build up the "configuration space" , EEPROM or SRAM , or either is ok ?
And what is the advantage of EEPROM and SRAM to build up for
the "configuration space" ? Can you help me to get a clear view of this
point ? Thank you very much , and sorry for interruping :)
----- Original Message -----
From: "MikeJ" <mikej@f... >
To: <pci@o... >
Date: Fri, 31 Aug 2001 23:48:45 +0100
Subject: Re: [pci] PCI target
> Tadej & people,
> Still alive !
>
> Sorry things have been quiet this month - I've been away longer
> than expected and have just got home.
> I have built a (prototype & simple - dummy backend i/f) virtex
> 300e-5 pci target which meets my draft 33mhz timespecs.
> However for faster speeds I strongly suspect I am going to have to
> use virtex specific cells which would have to be rloc'd.
> What are the general feelings about introducing vendor specific
> versions ?
>
> more news shortly.
> Mike
>
> ----- Original Message -----
> From: MikeJ
> To: pci@o...
> Sent: Saturday, July 28, 2001 10:25 PM
> Subject: Re: [pci] PCI target
>
> Tadej,
> Hi again.
> Things are going ok - I have a simple target integrated into a
> simulation model.
> However, It is hard to write generic vhdl (i.e. not instantiate
> xilinx specific stuff) or rloc's and still make 66mhz timing in a
> Virtex-e.
> I am being sent on a 2 week business trip, so progress will be slow
> for a bit - however I hope to check in a first attempt when I get
> back.
> Cheers,
>
> Mike.
>
>
> ----- Original Message -----
> From: Tadej
> To: pci@o...
> Sent: Wednesday, July 25, 2001 12:12 PM
> Subject: [pci] PCI target
>
> Hi Mike !
>
> What is the PCI Target module status? Do you have any problems
> regarding
> FIFOs and Wishbone interfaces, since you didn't design those
> modules?
> Maybe I can help.
> If there is anything not well explained, just let me know.
>
> Best regards,
> Tadej
>
>
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