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Message
From: "??" <flowers.yang@m...>
Date: Wed, 25 Jun 2003 23:01:11 +0800
Subject: [pci] Host Implement Reset
Hi, Guys:
After serveral days working on Opencore's PCI,
I have some question about cores
1) In pci bus monitor:
In Page 71 of PCI System Architecture, it says that
"While RST# is asserted, all masters must tri-state their REQ#
output drivers
and must ignore their GNT# inputs".
But the pci bus monitor seems requires that GNT# also tri-state
during reset ?
2) The pci bus monitor could not accept the bus parking ?
3) Under host implementation, when we use software reset. The reset
signals
would not disable or tristate the output.
For example, in the page 37 of PCI System Architecture, it suggests
that
AD, C/BE, PAR may be driven low during reset.
Although they are easily to be fixed. I am not sure what I do is correct
?
regards
flowers
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