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Message
From: Nico Weling <eedniwe@e...>
Date: Tue, 17 Jun 2003 10:30:56 +0200 (MEST)
Subject: [pci] TOP.v to TOP.sch
Hi,
I could successfully compile the PCI bridge and the card is seen by the system:
lspci : 02:0c.0 Bridge: Xilinx, Inc.: Unknown device 0001 (rev 01)
Then I create a symbol from the TOP.v file using Xilinx ISE 5.2 .
I directly connect exaclty the same ports to the symbol and use this schematic as my new TOP.sch
file.
Then I assign the working contrains file to TOP.sch.
This will successfully synthesize but the card is not be seen by the system (lspci)!
What did I wrong???
Regards/Nico.
P.S. The reason for doing this is because I'm not familiar with verilog, VHDL only ;-(. I like to
use the TOP schematic to add a WB slave (16bit D-Flipflop).
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