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Message
From: Joerg.Wille@e...
Date: Fri, 14 Mar 2003 14:19:29 +0100
Subject: [pci] a bunch of questions
Hi all,
I started a project with a friend of mine to develope a pci-audio card.
I now that this idea is not brand new one - but it's a starting point for
us.
We will start off with "simple" SPDIF I/O.
We are using the Spartan-II 200 PCI Evaluation Board from Memec
http://www.insight.na.memec.com/cgi-bin/bvutf8/memec/scripts/local/mc_loc_b.jsp?Div=INSIGHT&Reg=AMERICAS&Country=UNITED_STATES&Lang=EN&EDOID=187428&Manu=XILINX
and of course the OpenCores-PCI-Core.
I do have couple of questions:
- is someone doing the same thing like we are right now, who wants to share
some expirience with us?
- for our project, we won't need the WishBone. Has anyone already cut off
the WishBone-Part?
- if somebody uses the same Evaluation Board or the same Xilinx (XC2S200-5FG456C),
there might already exist a *.ucf place&route file.
- when systhesizing the verilog code of the pci-core in ise5.1 I get many
warnings
that the files pci-constants and user-constants are "redifined".
Is this correct and if so, what is the purpose of including this constants
in all files?
- after including the top.v module in ISE5.1 and adding all submodlules,
there are 2 red highlithed objects.
(vs_hdtp_64x40 two times) What kind of modules are these? i guess this
are memory modules.
But how can i include this modules to the project.
Thanks, Joerg.
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