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Message
From: "Miha Dolenc" <mihad@o...>
Date: Wed, 14 Aug 2002 09:01:33 +0200
Subject: Re: [pci] parity errors when simulation
Hi!
This happens because of testing purposes - we disable Parity Error Response
in PCI Bridge, generate wrong parity for address phase with behavioral pci
device and monitor SERR line which MUST NOT be asserted when Parity Error
Response is disabled. Monitor reports that condition. If you look at
*pci_mon.log simulation log file, you will see, that this errors are
enclosed in the "PCI Monitor complaining section". If this error occurs
outside this section, then this is an actual error.
Regards,
Miha Dolenc
----- Original Message -----
From: <random_user@1...>
To: <pci@o...>
Sent: Wednesday, August 14, 2002 6:23 AM
Subject: Re: [pci] parity errors when simulation
> Thanks for your answer!
> But it is reported by the pci_bus_monitor like this
> ***monitor - Undetected Address Parity Error ,Address `hc0000000,CBE
> `h7,PAR `h0
> since 'hc is 'h1100, 'h7 is 'h0111 so the totol number of 1 is 5,this
means
> an parity error occured.
>
> According to the pci_bus_monitor.v,only if the pci_ext_serr_l is '1' when
> an parity error occured,the monitor report the information like
> ***monitor ¡¡¡¡¡¡¡
>
> So ,I think it is some kind of error.Am I right?
>
> regards,
> wangc
>
> ----- Original Message -----
> From: "Miha Dolenc" <mihad@o... >
> To: <pci@o... >
> Date: Mon, 12 Aug 2002 10:08:17 +0200
> Subject: Re: [pci] parity errors when simulation
>
> >
> >
> > This is OK.
> > The testbench is intentionally causing this errors, to test the
> > functionality of parity generation and checking in the PCI Bridge.
> >
> > Regards,
> > Miha Dolenc
> >
> > ----- Original Message -----
> > From: <random_user@1... >
> > To: <pci@o... >
> > Sent: Monday, August 12, 2002 12:33 PM
> > Subject: [pci] parity errors when simulation
> >
> >
> > > When I tried to simulate the PCI core,the log file of VCS tell
> > me that
> > > there are some parity errors occured.
> > > 1.Invalid write data parity error
> > > 2.Undetected read data parity error
> > >
> > > I want to know whether I am simulating the core in a wrong
> > way.
> > > Any help will be appreciated!
> > >
> > > regards,
> > > wangc
> > >
> > >
> >
>
>
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