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Message
From: klm681@m...
Date: Tue, 30 Jul 2002 19:55:25 -0100
Subject: Re: [pci] PCI bus in Quartus II 2.0??????
We are not talking about the Altera IP core, I'm talking about the open
core PCI bus. The pci_mt64 is from Altera, not open source, correct?
----- Original Message -----
From: "Isa Servan Uzun" <isu@i... >
To: <pci@o... >
Date: Fri, 26 Jul 2002 08:39:21 +0300
Subject: Re: [pci] PCI bus in Quartus II 2.0??????
>
>
> I had no problem when I compile Altera pci_mt64 (66MHz/64-bit PCI)
> core
> in Quartus v1.1.
> I was also able to compile with Quartus 2.0, but I only have some
> timing
> violations
> because of the constraint file setting.
>
>
> ----- Original Message -----
> From: <klm681@m... >
> To: <pci@o... >
> Sent: Thursday, July 25, 2002 10:11 PM
> Subject: [pci] PCI bus in Quartus II 2.0??????
>
>
> > Has anyone compiled the PCI bus IP core using Quartus II 2.0
> software
> > from Altera? I tried, but I get this error message
> :"Unsupported Verilog
> > HDL feature error: parameter value assignment in module
> instatiation is
> > not supported". It appears like this line is causing problems
> :
> > WB_TPRAM #(`WB_FIFO_RAM_ADDR_LENGTH, 40) wbu_fifo_storage.
> > Any ideas? I don't really have the time to go through every
> module and
> > correct errors...
> >
> >
>
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