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    Navigation: All forums > Pci > Message List > Message Post

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    From: cfk <cfk@p...>
    Date: Mon, 17 Jun 2002 19:21:52 -0700
    Subject: Re: [pci] BUS Mastering & TRDY generation ?
    Top

    Dear Gustaw:
        Well, for the first time ever, I now can say that the PCI Wishbone
    bridge will generate TRDY when reading vendor/deviceID. I can now admire
    that fact that a transaction completes sufficient to see on my logic
    analyzer both a TRDY assertion by the bridge and the default vendor/deviceID
    at dword zero of "00012321". It is loaded into a Xilinx VirtexE 2000 chip. I
    can tell you that I had some trouble with the fact that the IDSEL needed to
    be set correctly. I did not get TRDY until the IDSEL was set to an address
    bit that my host was asserting. In my particular case, I am not using a PC,
    I have a vxWorks host connected directly to the bridge and I can see with
    the logic analyzer that it scans from AD[18]..AD[31]. I suspect that most
    motherboards do not scan AD[11]..AD[15] as I received an e-mail from a
    friend that told me the default setting of AD[11] in the testbench (which I
    used for my hardware) was wrong and the PCI spec indicates that PCI bridges
    talking to the PCI-Wishbone bridge will not scan AD[11]. So, all I can tell
    you is that it works, it reads configurations space back (at least dword
    zero), I'm tired and tomorrow is another day.
    
    Charles
    
    ----- Original Message -----
    From: <Gustaw47@p...>
    To: <pci@o...>
    Sent: Monday, June 17, 2002 8:17 AM
    Subject: [pci] BUS Mastering & TRDY generation ?
    
    
    > Hi all,
    >
    > I try to implement BUS Mastering on my PCI Card.
    > The card asserts REQ , Mainboard asserts GNT. Then I invoke addres
    > phase : Memory Read + some addres (tried different adresses), IRDY.
    > Mainboard still holds GNT (bus is mine) but never asserts TRDY so no
    > data can be transferred.
    > Finally I must deassert REQ and transaction fails to complete.
    >
    > What could be a reason that Mainboard doesn't assert TRDY ? I work in
    > the simplest enviroment : DOS, Real mode, software in ASM.
    >
    > The second question is:
    > If I use BAR Registers and reserve some MEMORY space for my card,
    > where phisically will it be located ? On mainboard's SD-RAM or in my
    > card's S-RAM ?
    >
    > Maybe I post trivial questions, but I didn't find any information about it
    > anywhere, even in PCI SIG Specifications ...
    >
    > Thanks in advance,
    > Gustaw Mazurek, Warsaw.
    > 
    >
    
    
    
    
    

    ReferenceAuthor
    [pci] BUS Mastering & TRDY generation ?Gustaw47

     
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