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Message
From: Mike Dini <mdini@d...>
Date: Mon, 13 May 2002 08:13:13 -0700
Subject: Re: [pci] why the address are grey coded?
At 08:51 AM 5/13/02 +0200, you wrote:
Hi!
Do you have an idea what the testcase
should be for the bug you found in the fifo?
I would like to add a testcase for every
bug that is found in the design, so it doesn't happen
again!
This is a good idea. Unfortunately, the error is related to how you
handled the grey-coded FIFO addresses as they crossed clock
boundaries. This doesn't lend itself to a simulation test
case. I might be able to generate a test-case using a
back-annotated simulation. I'll try. on the other hand, I may
be able to add some verilog 'display' lines to highlight the error if it
occurs.
Regards,
Miha Dolenc
- ----- Original Message -----
- From: Mike Dini
- To: pci@o...
- Cc:
mperry@d...
- Sent: Friday, May 10, 2002 6:35 PM
- Subject: Re: [pci] why the address are grey coded?
- At 08:30 AM 5/10/02 +0200, you wrote:
- The addresses are grey coded because it's an asynchronous fifo design.
- Normal binary counter comparison is only good for synchronous fifo designs.
- Actually this async fifo isn't quite correct in your open core. We are fixing now and will update you in a day or so.
- -----------------------------------------------------------
- Mike Dini Phone: (858) 454-3419 ext. 11
- President FAX: (858) 454-1728
- The DINI Group La Jolla cellular: (619) 888-9173
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- mdini@d... http://www.dinigroup.com
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