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Message
From: ezhcai@n...
Date: Thu, 28 Mar 2002 05:25:38 +0100
Subject: Re: [pci] why read is slower than write ?
Hi,
For read operation, the AD bus must have a turn-around cycle to ensure
there is no contention. So there is at least one wating cycle for a single
read operation, even you are implementing a fast-decode target. As for
write transfer, there is no such restriction, but for medium speed
address decode, there is also a wait state.
I've ever developed a simple revision 2.1 PCI target module with medium
speed decode, which can be fund at
www.ntu.edu.sg/home/ezhcai/IPdesign
It's a rough design, some signals need to be elaborated.
----- Original Message -----
From: Madhusudhan Rao <madhu_sudhana_rao@y... >
To: pci@o...
Date: Wed, 27 Mar 2002 19:54:45 -0800 (PST)
Subject: Re: [pci] why read is slower than write ?
>
>
> hi,
> Thanks for quick response. I am not talking about
> open cores. I developed by reading specification.
> I am implementing pci target. Let me expalin my doubt
> clearly.
> When i am reading data from ram(memory) it is taking 3
> cycles( 2 are wait cycles), but when i write any data
> on same memory it completing in a cycle witout any
> wait cycles. I don't have any FIFO's.
>
> Thanks in advance.
> Madhu
>
> --- Miha Dolenc <mihad@o... > wrote:
> > Hi!
> >
> > I don't know what you mean exactly! Are you talking
> > about OpenCores pci
> > bridge? Master or Target?
> > If you are referring to why PCI Target has 1 initial
> > wait cycle for reads
> > and none for writes, the reason is because outputs
> > must be registered.
> > Target has to pull data out of FIFO and put it in
> > output registers before
> > asserting TRDY.
> > Did this help?
> >
> > Regards,
> > Miha Dolenc
> >
> > ----- Original Message -----
> > From: "Madhusudhan Rao"
> > <madhu_sudhana_rao@y... >
> > To: <pci@o... >
> > Sent: Wednesday, March 27, 2002 11:11 AM
> > Subject: [pci] why read is slower than write ?
> >
> >
> > > Hi,
> > > When i am implementing pci memory read
> > transactions
> > > i was in a need of keeping 2 wait cycles for
> > proper
> > > read operation but for write with 1 clock cycle i
> > am
> > > able to memory write. what may be the reason can
> > any
> > > body give suggestions. All kinds of inputs are
> > > welcome.
> > >
> > > Thanks in advance
> > > Madhu
> > >
> > >
> > > =====
> > > MadhusudhanaRao.M
> > >
> > > __________________________________________________
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> > >
> >
> >
> >
>
>
> =====
> MadhusudhanaRao.M
>
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