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Message
From: sky@v...
Date: Thu, 7 Mar 2002 10:48:17 +0100
Subject: [pci] RE: [pci] Problems compiling PCI core and test bench for Modelsim
I've encountered some problems like yours. Now I try to modify sintax of
some blocks to compile files with "vcom".
I hope to be able to do this because pci core is a chip way to obtain a
good pci interface with a standard local intarface.
If I obtain some good results I'll tell you.
good work
Massimo
-- Messaggio originale --
>All:
>
>I am trying to compile this project with Modelsim and I get the following
>errors. I downloaded the entire project and used the attached script to
>compile. The compile.log file is my errors. I can fix the errors, but
this
>is making me wonder if I am missing something or have out of date files.
> I have never used verilog before, but the free PCI core is very appealing
>so I thought I would evaluate it. Any help would be much appreciated.
>
>Thanks,
>
>Jim
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