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Message
From: "rama mohan" <ramu_pci@h...>
Date: Wed, 06 Feb 2002 17:59:48 -0800
Subject: Re: [pci] burst data phase.
hay runner,
Thanks for ur response. What u told i did same thing. My question is
when i want to implement burst data transfer. what i have to do extra logic
than when we develop single data phase transactions.
Thanks once again.
All kinds of suggestions are appreciated.
Thanks
Ramu
>From: runner <runner@z...>
>Reply-To: pci@o...
>To: "pci@o..." <pci@o...>
>Subject: Re: [pci] burst data phase.
>Date: Thu, 7 Feb 2002 8:45:21 +0800
>
>rama mohan£¬
> the master needn't to know how mang cycles to maintain. in single date
>transfer mode, the FRAME#(driven by master) will maintain active until the
>target asserts the TARRDY# or STOP#. That's to say FRAME# is driven active
>when master need to get/receive data and deasserted when it finishes the
>data phase.
>
>
>
> >pci gurus,
> > I have devoleped pci 32 bit 33 mhz core with single data phase
> >transaction facility only. I would like to add the burst data phases
> >feature. I am devoleping that. But i strucked at one point.
> >How master come to know that for how many clock cycles to maintain frame.
> >Any body can give me suggestions.
> >All kinds of suggestions are appreciated.
> >
> >thanks in advance
> >
> >ramu
> >
>http://explorer.msn.com/intl.asp.
> >
> >
>
>
> runner
> runner@z...
>
>
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