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Dear all,

Avi Blanka wrote:
Hi Avi
This questions should be in the openrisc@o... mailing list.
> Dear all,
>  
> Is any body used Or1k and can help me by answering to this questions:
>  
> 1. Can you please advise how to arrange the code image? (How to 
> arrange ram.ld file).
>  

This depends on how you arranged SDRAM/SRAM/FLASH

> 2. Is there a tool for conversion the build output into a file that 
> can be loaded into the board?
>     Is there a specific tool for conversion to Xilinx ram format?

You can use GDB to and JTAG software (JP1/JP2) to load program.

>  
> 3. In some code samples there is a reset.S file which implements reset 
> starting from address 0x100
>     How does it suit the ram.ld declarations?

You have to tell the linker to put the first code ( _reset ) at address 
0x100
This is done in the reset code

        .section .vectors, "ax"
        .org 0x100
_reset:
        l.movhi r1,hi(_stack-4)
        l.ori   r1,r1,lo(_stack-4)
        ...

>  
> 4. What is the sequence that causes the CPU to jump to first code 
> instruction declared in ram.ld file? 

ram.ld is a set of instructions to the linker of how to link code and data.
After CPU reset, an exception is thrown and the PC is set to address 
0x0000100 or 0xF000100 (depend on SR register)

Regards,
Nir

>  
> Regards,
> Avi Blanka
>
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