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Message
From: cvs at opencores.org<cvs@o...>
Date: Sat Jul 26 21:15:33 CEST 2008
Subject: [cvs-checkins] MODIFIED: wb_lpc ...
Date: 00/08/07 26:21:15 Modified: wb_lpc/sim/wb_lpc_sim tb_lpc_top.v wb_lpc_sim.ise
Log:
Fix bugs:
25-Jul-2008 LPC firmware writes must not insert wait-states.
22-Jul-2008 LPC DMA does not report READY+MORE for multi-byte transfers
Add feature:
23-Jul-2008 propagate Wishbone errors across LPC interface
Improve Testbench:
Ability to test multiple wait-states on LPC Peripheral Wishbone Master interface.
Check wbs_err_o from LPC Host.
Rebuild examples with the fixes above.
Revision Changes Path
1.2 wb_lpc/sim/wb_lpc_sim/tb_lpc_top.v
http://www.opencores.org/cvsweb.shtml/wb_lpc/sim/wb_lpc_sim/tb_lpc_top.v.diff?r1=1.1&r2=1.2
(In the diff below, changes in quantity of whitespace are not shown.)
Index: tb_lpc_top.v
===================================================================
RCS file: /cvsroot/hharte/wb_lpc/sim/wb_lpc_sim/tb_lpc_top.v,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- tb_lpc_top.v 2 Mar 2008 20:46:41 -0000 1.1
+++ tb_lpc_top.v 26 Jul 2008 19:15:32 -0000 1.2
@@ -59,6 +59,7 @@
// LPC Host Outputs
wire [31:0] wbs_dat_o;
wire wbs_ack_o;
+ wire wbs_err_o;
wire lframe_o;
wire [3:0] lad_o;
wire lad_oe;
@@ -69,6 +70,7 @@
// LPC Peripheral Inputs
wire [31:0] wbm_dat_i;
wire wbm_ack_i;
+ wire wbm_err_i;
// LPC Peripheral Outputs
wire [31:0] wbm_adr_o;
@@ -86,6 +88,8 @@
reg dma_req_i;
+ reg [7:0] regfile_ws;
+
task Reset;
begin
nrst_i = 1; # 1000;
@@ -99,6 +103,7 @@
input reg [31:0] adr_i;
input reg [3:0] sel_i;
input reg [31:0] dat_i;
+ input reg expect_err;
reg [7:0] wait_cnt;
begin
@@ -111,21 +116,38 @@
wait_cnt = 0;
- while ((wbs_ack_o == 0) & (wait_cnt < 100))
+ while ((wbs_ack_o == 0) & (wait_cnt < 1000))
begin
wait_cnt = wait_cnt+1;
# 100;
end
- if(wait_cnt == 100)
+ if(wait_cnt == 1000)
begin
$display($time, " Error, wb_w[%x/%x]: timeout waiting for ack", adr_i, dat_i); $stop(1);
end
+ if(expect_err != wbs_err_o)
+ begin
+ $display($time, " Error: wb_w[%x/%x]: wb_err_o is %d, expected %d", adr_i, dat_i, wbs_err_o, expect_err); $stop(1);
+ end
wbs_stb_i = 1'b0;
wbs_cyc_i = 1'b0;
wbs_we_i = 1'b0;
+ wait_cnt = 0;
+
+ while ((wbs_ack_o == 1) & (wait_cnt < 100))
+ begin
+ wait_cnt = wait_cnt+1;
+ # 100;
+ end
+
+ if(wait_cnt == 100)
+ begin
+ $display($time, " Error, wb_w[%x]: timeout waiting for ack to go away", adr_i); $stop(1);
+ end
+
end
endtask
@@ -134,6 +156,7 @@
input reg [31:0] adr_i;
input reg [3:0] sel_i;
input reg [31:0] dat_i;
+ input reg expect_err;
reg [7:0] wait_cnt;
begin
@@ -146,13 +169,13 @@
wait_cnt = 0;
- while ((wbs_ack_o == 0) & (wait_cnt < 100))
+ while ((wbs_ack_o == 0) & (wait_cnt < 1000))
begin
wait_cnt = wait_cnt+1;
# 100;
end
- if(wait_cnt == 100)
+ if(wait_cnt == 1000)
begin
$display($time, " Error, wb_r[%x]: timeout waiting for ack", adr_i); $stop(1);
end
@@ -160,12 +183,32 @@
wbs_stb_i = 1'b0;
wbs_cyc_i = 1'b0;
+ if(expect_err != wbs_err_o)
+ begin
+ $display($time, " Error: wb_r[%x/%x]: wb_err_o is %d, expected %d", adr_i, dat_i, wbs_err_o, expect_err); $stop(1);
+ end
+
+ if(wbs_err_o == 0) begin
if(dat_i != wbs_dat_o)
begin
$display($time, " Error, wb_r[%x]: expected %x, got %x", adr_i, dat_i, wbs_dat_o); $stop(1);
end
+ end
+
+ wait_cnt = 0;
+
+ while ((wbs_ack_o == 1) & (wait_cnt < 100))
+ begin
+ wait_cnt = wait_cnt+1;
+ # 100;
+ end
+ if(wait_cnt == 100)
+ begin
+ $display($time, " Error, wb_r[%x]: timeout waiting for ack to go away", adr_i); $stop(1);
end
+end
+
endtask
@@ -187,6 +230,7 @@
.wbs_stb_i(wbs_stb_i),
.wbs_cyc_i(wbs_cyc_i),
.wbs_ack_o(wbs_ack_o),
+ .wbs_err_o(wbs_err_o),
.dma_chan_i(dma_chan_i),
.dma_tc_i(dma_tc_i),
.lframe_o(lframe_o),
@@ -208,6 +252,7 @@
.wbm_stb_o(wbm_stb_o),
.wbm_cyc_o(wbm_cyc_o),
.wbm_ack_i(wbm_ack_i),
+ .wbm_err_i(wbm_err_i),
.dma_chan_o(dma_chan_o),
.dma_tc_o(dma_tc_o),
.lframe_i(lframe_o),
@@ -245,7 +290,7 @@
wb_regfile regfile (
.clk_i(clk_i),
.nrst_i(nrst_i),
- .wb_adr_i(wbm_adr_o),
+ .wb_adr_i(dma_chan_i == 2 ? 32'h00000008 : wbm_adr_o),
.wb_dat_o(wbm_dat_i),
.wb_dat_i(wbm_dat_o),
.wb_sel_i(wbm_sel_o),
@@ -253,6 +298,8 @@
.wb_stb_i(wbm_stb_o),
.wb_cyc_i(wbm_cyc_o),
.wb_ack_o(wbm_ack_i),
+ .wb_err_o(wbm_err_i),
+ .ws_i(regfile_ws),
.datareg0(datareg0),
.datareg1(datareg1)
);
@@ -277,146 +324,137 @@
dma_chan_i = 3'b0;
dma_tc_i = 0;
dma_req_i = 0;
-
+ regfile_ws = 8'h0; // Number of wait-states (0-255)
Reset();
-
+ $display($time, " * * * Using %d peripheral-side wait-states for this test.", regfile_ws);
wbs_tga_i = `WB_TGA_IO;
$display($time, " Testing LPC I/O Accesses");
- wb_write(32'h00000000, `WB_SEL_BYTE, 32'h00000012);
- # 100;
- wb_write(32'h00000001, `WB_SEL_BYTE, 32'h00000034);
- # 100;
- wb_write(32'h00000002, `WB_SEL_BYTE, 32'h00000056);
- # 100;
- wb_write(32'h00000003, `WB_SEL_BYTE, 32'h00000078);
- # 100;
- wb_write(32'h00000004, `WB_SEL_BYTE, 32'h0000009a);
- # 100;
- wb_write(32'h00000005, `WB_SEL_BYTE, 32'h000000bc);
- # 100;
- wb_write(32'h00000006, `WB_SEL_BYTE, 32'h000000de);
- # 100;
- wb_write(32'h00000007, `WB_SEL_BYTE, 32'h000000f0);
- # 100;
-
- wb_read(32'h00000000, `WB_SEL_BYTE, 32'hXXXXXX12);
- # 100;
- wb_read(32'h00000001, `WB_SEL_BYTE, 32'hXXXXXX34);
- # 100;
- wb_read(32'h00000002, `WB_SEL_BYTE, 32'hXXXXXX56);
- # 100;
- wb_read(32'h00000003, `WB_SEL_BYTE, 32'hXXXXXX78);
- # 100;
- wb_read(32'h00000004, `WB_SEL_BYTE, 32'hXXXXXX9a);
- # 100;
- wb_read(32'h00000005, `WB_SEL_BYTE, 32'hXXXXXXbc);
- # 100;
- wb_read(32'h00000006, `WB_SEL_BYTE, 32'hXXXXXXde);
- # 100;
- wb_read(32'h00000007, `WB_SEL_BYTE, 32'hXXXXXXf0);
- # 100;
-
+ wb_write(32'h00000000, `WB_SEL_BYTE, 32'h00000012, 0);
+ wb_write(32'h00000001, `WB_SEL_BYTE, 32'h00000034, 0);
+ wb_write(32'h00000002, `WB_SEL_BYTE, 32'h00000056, 0);
+ wb_write(32'h00000003, `WB_SEL_BYTE, 32'h00000078, 0);
+ wb_write(32'h00000004, `WB_SEL_BYTE, 32'h0000009a, 0);
+ wb_write(32'h00000005, `WB_SEL_BYTE, 32'h000000bc, 0);
+ wb_write(32'h00000006, `WB_SEL_BYTE, 32'h000000de, 0);
+ wb_write(32'h00000007, `WB_SEL_BYTE, 32'h000000f0, 0);
+
+ wb_read(32'h00000000, `WB_SEL_BYTE, 32'hXXXXXX12, 0);
+ wb_read(32'h00000001, `WB_SEL_BYTE, 32'hXXXXXX34, 0);
+ wb_read(32'h00000002, `WB_SEL_BYTE, 32'hXXXXXX56, 0);
+ wb_read(32'h00000003, `WB_SEL_BYTE, 32'hXXXXXX78, 0);
+ wb_read(32'h00000004, `WB_SEL_BYTE, 32'hXXXXXX9a, 0);
+ wb_read(32'h00000005, `WB_SEL_BYTE, 32'hXXXXXXbc, 0);
+ wb_read(32'h00000006, `WB_SEL_BYTE, 32'hXXXXXXde, 0);
+ wb_read(32'h00000007, `WB_SEL_BYTE, 32'hXXXXXXf0, 0);
wbs_tga_i = `WB_TGA_MEM;
$display($time, " Testing LPC MEM Accesses");
- wb_write(32'h00000000, `WB_SEL_BYTE, 32'h00000012);
- # 100;
- wb_write(32'h00000001, `WB_SEL_BYTE, 32'h00000034);
- # 100;
- wb_write(32'h00000002, `WB_SEL_BYTE, 32'h00000056);
- # 100;
- wb_write(32'h00000003, `WB_SEL_BYTE, 32'h00000078);
- # 100;
- wb_write(32'h00000004, `WB_SEL_BYTE, 32'h0000009a);
- # 100;
- wb_write(32'h00000005, `WB_SEL_BYTE, 32'h000000bc);
- # 100;
- wb_write(32'h00000006, `WB_SEL_BYTE, 32'h000000de);
- # 100;
- wb_write(32'h00000007, `WB_SEL_BYTE, 32'h000000f0);
- # 100;
-
- wb_read(32'h00000000, `WB_SEL_BYTE, 32'hXXXXXX12);
- # 100;
- wb_read(32'h00000001, `WB_SEL_BYTE, 32'hXXXXXX34);
- # 100;
- wb_read(32'h00000002, `WB_SEL_BYTE, 32'hXXXXXX56);
- # 100;
- wb_read(32'h00000003, `WB_SEL_BYTE, 32'hXXXXXX78);
- # 100;
- wb_read(32'h00000004, `WB_SEL_BYTE, 32'hXXXXXX9a);
- # 100;
- wb_read(32'h00000005, `WB_SEL_BYTE, 32'hXXXXXXbc);
- # 100;
- wb_read(32'h00000006, `WB_SEL_BYTE, 32'hXXXXXXde);
- # 100;
- wb_read(32'h00000007, `WB_SEL_BYTE, 32'hXXXXXXf0);
- # 100;
+ wb_write(32'h00000000, `WB_SEL_BYTE, 32'h00000012, 0);
+ wb_write(32'h00000001, `WB_SEL_BYTE, 32'h00000034, 0);
+ wb_write(32'h00000002, `WB_SEL_BYTE, 32'h00000056, 0);
+ wb_write(32'h00000003, `WB_SEL_BYTE, 32'h00000078, 0);
+ wb_write(32'h00000004, `WB_SEL_BYTE, 32'h0000009a, 0);
+ wb_write(32'h00000005, `WB_SEL_BYTE, 32'h000000bc, 0);
+ wb_write(32'h00000006, `WB_SEL_BYTE, 32'h000000de, 0);
+ wb_write(32'h00000007, `WB_SEL_BYTE, 32'h000000f0, 0);
+
+ wb_read(32'h00000000, `WB_SEL_BYTE, 32'hXXXXXX12, 0);
+ wb_read(32'h00000001, `WB_SEL_BYTE, 32'hXXXXXX34, 0);
+ wb_read(32'h00000002, `WB_SEL_BYTE, 32'hXXXXXX56, 0);
+ wb_read(32'h00000003, `WB_SEL_BYTE, 32'hXXXXXX78, 0);
+ wb_read(32'h00000004, `WB_SEL_BYTE, 32'hXXXXXX9a, 0);
+ wb_read(32'h00000005, `WB_SEL_BYTE, 32'hXXXXXXbc, 0);
+ wb_read(32'h00000006, `WB_SEL_BYTE, 32'hXXXXXXde, 0);
+ wb_read(32'h00000007, `WB_SEL_BYTE, 32'hXXXXXXf0, 0);
wbs_tga_i = `WB_TGA_DMA;
$display($time, " Testing LPC DMA BYTE Accesses");
dma_chan_i = 3'h1;
- wb_write(32'h00000000, `WB_SEL_BYTE, 32'hXXXXXX21);
- # 100;
-
- wb_read(32'h00000000, `WB_SEL_BYTE, 32'hXXXXXX21);
- # 100;
+ wb_write(32'h00000000, `WB_SEL_BYTE, 32'hXXXXXX21, 0);
+ wb_read(32'h00000000, `WB_SEL_BYTE, 32'hXXXXXX21, 0);
$display($time, " Testing LPC DMA SHORT Accesses");
dma_chan_i = 3'h3;
- wb_write(32'h00000000, `WB_SEL_SHORT, 32'hXXXX6543);
- # 100;
-
- wb_read(32'h00000000, `WB_SEL_SHORT, 32'hXXXX6543);
- # 100;
+ wb_write(32'h00000000, `WB_SEL_SHORT, 32'hXXXX6543, 0);
+ wb_read(32'h00000000, `WB_SEL_SHORT, 32'hXXXX6543, 0);
$display($time, " Testing LPC DMA WORD Accesses");
dma_chan_i = 3'h7;
- wb_write(32'h00000000, `WB_SEL_WORD, 32'hedcba987);
- # 100;
-
- wb_read(32'h00000000, `WB_SEL_WORD, 32'hedcba987);
- # 100;
+ wb_write(32'h00000000, `WB_SEL_WORD, 32'hedcba987, 0);
+ wb_read(32'h00000000, `WB_SEL_WORD, 32'hedcba987, 0);
+ dma_chan_i = 3'h0;
wbs_tga_i = `WB_TGA_FW;
$display($time, " Testing LPC Firmwre BYTE Accesses");
- dma_chan_i = 3'h1;
- wb_write(32'h00000000, `WB_SEL_BYTE, 32'hXXXXXX12);
- # 100;
-
- wb_read(32'h00000000, `WB_SEL_BYTE, 32'hXXXXXX12);
- # 100;
+ wb_write(32'h00000000, `WB_SEL_BYTE, 32'hXXXXXX12, 0);
+ wb_read(32'h00000000, `WB_SEL_BYTE, 32'hXXXXXX12, 0);
$display($time, " Testing LPC Firmware SHORT Accesses");
- dma_chan_i = 3'h3;
- wb_write(32'h00000000, `WB_SEL_SHORT, 32'hXXXX3456);
- # 100;
-
- wb_read(32'h00000000, `WB_SEL_SHORT, 32'hXXXX3456);
- # 100;
+ wb_write(32'h00000000, `WB_SEL_SHORT, 32'hXXXX3456, 0);
+ wb_read(32'h00000000, `WB_SEL_SHORT, 32'hXXXX3456, 0);
$display($time, " Testing LPC Firmware WORD Accesses");
- dma_chan_i = 3'h7;
- wb_write(32'h00000000, `WB_SEL_WORD, 32'h789abcde);
- # 100;
+ wb_write(32'h00000000, `WB_SEL_WORD, 32'h789abcde, 0);
+ wb_read(32'h00000000, `WB_SEL_WORD, 32'h789abcde, 0);
- wb_read(32'h00000000, `WB_SEL_WORD, 32'h789abcde);
- # 100;
+ dma_chan_i = 3'h0;
+ // Test Wishbone transfers that complete with an error.
+ // This should abort the LPC access in progress and return
+ // a Wishbone error at the host. Note that Wishbone will
+ // detect the bus error when the wishbone master on the
+ // LPC peripheral attempts the Wishbone transfer. For LPC
+ // reads (peripheral to host,) this will be during the
+ // first byte of the LPC transfer. For LPC writes (host
+ // to peripheral,) the Wishbone cycle is initiated when
+ // the last byte of the LPC access is transferred.
+ wbs_tga_i = `WB_TGA_IO;
+ $display($time, " Testing LPC I/O Accesses (with Wishbone error)");
+ wb_write(32'h00000008, `WB_SEL_BYTE, 32'h00000012, 1);
+ wb_read(32'h00000008, `WB_SEL_BYTE, 32'hXXXXXX12, 1);
- dma_req_i = 1;
- # 100
- dma_req_i = 0;
- # 1000;
+ wbs_tga_i = `WB_TGA_MEM;
+ $display($time, " Testing LPC MEM Accesses (with Wishbone error)");
+ wb_write(32'h00000008, `WB_SEL_BYTE, 32'h00000012, 1);
+ wb_read(32'h00000008, `WB_SEL_BYTE, 32'hXXXXXX12, 1);
- dma_chan_i = 3'b101;
+ wbs_tga_i = `WB_TGA_DMA;
- dma_req_i = 1;
- # 100
- dma_req_i = 0;
- # 1000;
+ $display($time, " Testing LPC DMA BYTE Accesses (with Wishbone error)");
+ // DMA channel 2 is a special case, using this channel will cause an
+ // error on the Wishbone backplane.
+ dma_chan_i = 3'h2;
+ wb_write(32'h00000008, `WB_SEL_BYTE, 32'hXXXXXX21, 1);
+ wb_read(32'h00000008, `WB_SEL_BYTE, 32'hXXXXXX21, 1);
+
+ $display($time, " Testing LPC DMA SHORT Accesses (with Wishbone error)");
+ dma_chan_i = 3'h2;
+ wb_write(32'h00000008, `WB_SEL_SHORT, 32'hXXXX6543, 1);
+ wb_read(32'h00000008, `WB_SEL_SHORT, 32'hXXXX6543, 1);
+
+ $display($time, " Testing LPC DMA WORD Accesses (with Wishbone error)");
+ dma_chan_i = 3'h2;
+ wb_write(32'h00000008, `WB_SEL_WORD, 32'hedcba987, 1);
+ wb_read(32'h00000008, `WB_SEL_WORD, 32'hedcba987, 1);
+
+ dma_chan_i = 3'h0;
+ wbs_tga_i = `WB_TGA_FW;
+ // Firmware accesses cannot generate an error, according to the LPC spec;
+ // however, the wishbone write will fail, so the subsequent read
+ // will return bad data, so we just don't check the read data.
+ $display($time, " Testing LPC Firmwre BYTE Accesses (with Wishbone error)");
+ wb_write(32'h00000008, `WB_SEL_BYTE, 32'hXXXXXX12, 0);
+ wb_read(32'h00000008, `WB_SEL_BYTE, 32'hXXXXXXXX, 0);
+
+ $display($time, " Testing LPC Firmware SHORT Accesses (with Wishbone error)");
+ wb_write(32'h00000008, `WB_SEL_SHORT, 32'hXXXX3456, 0);
+ wb_read(32'h00000008, `WB_SEL_SHORT, 32'hXXXXXXXX, 0);
+
+ $display($time, " Testing LPC Firmware WORD Accesses (with Wishbone error)");
+ wb_write(32'h00000008, `WB_SEL_WORD, 32'h789abcde, 0);
+ wb_read(32'h00000008, `WB_SEL_WORD, 32'hXXXXXXXX, 0);
$display($time, " Simulation passed"); $stop(1);
1.4 wb_lpc/sim/wb_lpc_sim/wb_lpc_sim.ise
http://www.opencores.org/cvsweb.shtml/wb_lpc/sim/wb_lpc_sim/wb_lpc_sim.ise?rev=1.4&content-type=text/x-cvsweb-markup
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