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Message
From: cvs at opencores.org<cvs@o...>
Date: Sat Jul 26 09:29:32 CEST 2008
Subject: [cvs-checkins] MODIFIED: ethernet_tri_mode ...
Date: 00/08/07 26:09:29 Added: ethernet_tri_mode/sim/rtl_sim/modsim_sim/bin com.mod
ip_32W_check.dll ip_32W_gen.dll sim.mod
vlog-rtl.list
Log:
no message
Revision Changes Path
1.1 ethernet_tri_mode/sim/rtl_sim/modsim_sim/bin/com.mod
http://www.opencores.org/cvsweb.shtml/ethernet_tri_mode/sim/rtl_sim/modsim_sim/bin/com.mod?rev=1.1&content-type=text/x-cvsweb-markup
Index: com.mod
===================================================================
if test -d work
then
echo work is ready
else
vlib work
echo work is created
fi
vlog -f vlog-$1.list
if test $? -ne 0
then
echo compiling err occured...
exit 1
fi
1.1 ethernet_tri_mode/sim/rtl_sim/modsim_sim/bin/ip_32W_check.dll
http://www.opencores.org/cvsweb.shtml/ethernet_tri_mode/sim/rtl_sim/modsim_sim/bin/ip_32W_check.dll?rev=1.1&content-type=text/x-cvsweb-markup
<<Binary file>>
1.1 ethernet_tri_mode/sim/rtl_sim/modsim_sim/bin/ip_32W_gen.dll
http://www.opencores.org/cvsweb.shtml/ethernet_tri_mode/sim/rtl_sim/modsim_sim/bin/ip_32W_gen.dll?rev=1.1&content-type=text/x-cvsweb-markup
<<Binary file>>
1.1 ethernet_tri_mode/sim/rtl_sim/modsim_sim/bin/sim.mod
http://www.opencores.org/cvsweb.shtml/ethernet_tri_mode/sim/rtl_sim/modsim_sim/bin/sim.mod?rev=1.1&content-type=text/x-cvsweb-markup
Index: sim.mod
===================================================================
if test -d work
then
echo work is ready
else
vlib work
echo work is created
fi
vlog -f vlog-$1.list
if test $? -ne 0
then
echo compiling err occured...
exit 1
fi
if [ $1 = rtl ]
then
vsim tb_top -pli ip_32W_gen.dll -pli ip_32W_check.dll $2 -do "run -all"
else
vsim glbl tb_top -pli ip_32W_gen.dll -pli ip_32W_check.dll
fi
1.1 ethernet_tri_mode/sim/rtl_sim/modsim_sim/bin/vlog-rtl.list
http://www.opencores.org/cvsweb.shtml/ethernet_tri_mode/sim/rtl_sim/modsim_sim/bin/vlog-rtl.list?rev=1.1&content-type=text/x-cvsweb-markup
Index: vlog-rtl.list
===================================================================
../../../../rtl/verilog/header.v
../../../../rtl/verilog/TECH/CLK_SWITCH.v
../../../../rtl/verilog/TECH/CLK_DIV2.v
../../../../rtl/verilog/TECH/duram.v
../../../../rtl/verilog/MAC_tx/MAC_tx_FF.v
../../../../rtl/verilog/MAC_tx/Ramdon_gen.v
../../../../rtl/verilog/MAC_tx/CRC_gen.v
../../../../rtl/verilog/MAC_tx/MAC_tx_addr_add.v
../../../../rtl/verilog/MAC_tx/MAC_tx_Ctrl.v
../../../../rtl/verilog/MAC_tx/flow_ctrl.v
../../../../rtl/verilog/MAC_rx/CRC_chk.v
../../../../rtl/verilog/MAC_rx/MAC_rx_add_chk.v
../../../../rtl/verilog/MAC_rx/MAC_rx_FF.v
../../../../rtl/verilog/MAC_rx/MAC_rx_ctrl.v
../../../../rtl/verilog/MAC_rx/Broadcast_filter.v
../../../../rtl/verilog/miim/eth_clockgen.v
../../../../rtl/verilog/miim/eth_outputcontrol.v
../../../../rtl/verilog/miim/eth_shiftreg.v
../../../../rtl/verilog/RMON/RMON_addr_gen.v
../../../../rtl/verilog/RMON/RMON_ctrl.v
../../../../rtl/verilog/RMON/RMON_dpram.v
../../../../rtl/verilog/RMON.v
../../../../rtl/verilog/MAC_rx.v
../../../../rtl/verilog/MAC_tx.v
../../../../rtl/verilog/eth_miim.v
../../../../rtl/verilog/MAC_top.v
../../../../rtl/verilog/Phy_int.v
../../../../rtl/verilog/Clk_ctrl.v
../../../../rtl/verilog/Reg_int.v
../../../../bench/verilog/altera_mf.v
../../../../bench/verilog/Phy_sim.v
../../../../bench/verilog/User_int_sim.v
../../../../bench/verilog/host_sim.v
../../../../bench/verilog/tb_top.v
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