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From: cvs at opencores.org<cvs@o...>
Date: Thu Jul 24 19:28:26 CEST 2008
Subject: [cvs-checkins] MODIFIED: jop ...
Date: 00/08/07 24:19:28

Modified: jop/vhdl/top jop_ml401a.vhd jop_ml401.vhd
jop_config_ml401.vhd
Log:
Frequency halved


Revision Changes Path
1.2 jop/vhdl/top/jop_ml401a.vhd

http://www.opencores.org/cvsweb.shtml/jop/vhdl/top/jop_ml401a.vhd.diff?r1=1.1&r2=1.2

(In the diff below, changes in quantity of whitespace are not shown.)

Index: jop_ml401a.vhd
===================================================================
RCS file: /cvsroot/jwhitham/jop/vhdl/top/jop_ml401a.vhd,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- jop_ml401a.vhd 22 Jul 2008 12:11:40 -0000 1.1
+++ jop_ml401a.vhd 24 Jul 2008 17:28:26 -0000 1.2
@@ -108,7 +108,7 @@
--
-- Signals
--
- signal clk_int : std_logic;
+ signal clk_int, clk2 : std_logic;

signal int_res : std_logic;
signal res_cnt : unsigned(2 downto 0) := "000"; -- for the simulation
@@ -162,18 +162,20 @@

signal sc_arb_out : arb_out_type(0 to master_cnt-1);
signal sc_arb_in : arb_in_type(0 to master_cnt-1);
+
+ signal io_r : std_logic_vector(20 downto 1);
begin

--================================================--
--============VIRTEX 4 SRAM SIGNALS===============--

-sram_feedback_clk <= not clk;
+sram_feedback_clk <= not clk2;
sram_adv_ld_n <= '0';
sram_mode <= '0';
sram_cen <= '0';
virtex_ram_addr <= "00000" & ram_addr;
sram_zz <= '0';
-sram_clk <= not clk;
+sram_clk <= not clk2;
--================================================--
--================================================--

@@ -196,6 +198,13 @@
end if;
end process;

+process(clk)
+begin
+ if rising_edge(clk) then
+ clk2 <= not clk2;
+ end if;
+end process;
+
cp1 : entity mac_coprocessor
generic map ( id => x"01", version => x"1234" )
port map (
@@ -235,7 +244,7 @@
--
-- components of jop
--
- clk_int <= clk;
+ clk_int <= clk2;

wd <= wd_out;

@@ -271,7 +280,7 @@
nrts => ser_nrts,
wd => wd_out,
l => open,
- r => open,
+ r => io_r,
t => open,
b => open,

@@ -313,6 +322,9 @@
end if;
end process;

+ io_r ( 9 ) <= '1' ;
+ io_r ( 10 ) <= '1' ;
+
ram_din <= ramb_d & rama_d;

--



1.6 jop/vhdl/top/jop_ml401.vhd

http://www.opencores.org/cvsweb.shtml/jop/vhdl/top/jop_ml401.vhd.diff?r1=1.5&r2=1.6 (In the diff below, changes in quantity of whitespace are not shown.) Index: jop_ml401.vhd =================================================================== RCS file: /cvsroot/jwhitham/jop/vhdl/top/jop_ml401.vhd,v retrieving revision 1.5 retrieving revision 1.6 diff -u -b -r1.5 -r1.6 --- jop_ml401.vhd 4 Mar 2008 19:32:58 -0000 1.5 +++ jop_ml401.vhd 24 Jul 2008 17:28:26 -0000 1.6 @@ -128,7 +128,7 @@ -- -- Signals -- - signal clk_int : std_logic; + signal clk_int, clk2 : std_logic; signal int_res : std_logic; signal res_cnt : unsigned(2 downto 0) := "000"; -- for the simulation @@ -172,13 +172,13 @@ --================================================-- --============VIRTEX 4 SRAM SIGNALS===============-- -sram_feedback_clk <= not clk; +sram_feedback_clk <= not clk2; sram_adv_ld_n <= '0'; sram_mode <= '0'; sram_cen <= '0'; virtex_ram_addr <= "00000" & ram_addr; sram_zz <= '0'; -sram_clk <= not clk; +sram_clk <= not clk2; --================================================-- --================================================-- @@ -198,11 +198,17 @@ int_res <= not res_cnt(0) or not res_cnt(1) or not res_cnt(2); end if; end process; +process(clk) +begin + if rising_edge(clk) then + clk2 <= not clk2; + end if; +end process; -- -- components of jop -- - clk_int <= clk; + clk_int <= clk2; wd <= wd_out; 1.4 jop/vhdl/top/jop_config_ml401.vhd http://www.opencores.org/cvsweb.shtml/jop/vhdl/top/jop_config_ml401.vhd.diff?r1=1.3&r2=1.4 (In the diff below, changes in quantity of whitespace are not shown.) Index: jop_config_ml401.vhd =================================================================== RCS file: /cvsroot/jwhitham/jop/vhdl/top/jop_config_ml401.vhd,v retrieving revision 1.3 retrieving revision 1.4 diff -u -b -r1.3 -r1.4 --- jop_config_ml401.vhd 23 Feb 2008 23:18:47 -0000 1.3 +++ jop_config_ml401.vhd 24 Jul 2008 17:28:26 -0000 1.4 @@ -30,7 +30,7 @@ package jop_config is - constant clk_freq : integer := 100000000; + constant clk_freq : integer := 100000000/2; -- constant for on-chip memory constant ram_width : integer := 8; -- address bits of internal ram (sp,...)