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From: cvs at opencores.org<cvs@o...>
Date: Tue Jul 22 15:46:43 CEST 2008
Subject: [cvs-checkins] MODIFIED: wb_lpc ...
Date: 00/08/07 22:15:46

Modified: wb_lpc/rtl/verilog wb_lpc_host.v wb_lpc_periph.v
Log:
fixed bug: Spec vviolation for multi-byte firmware amcesses:

the multi-byte firmware accesses incorrectly follow the multi-byte DMA algorithm and issue a SYNC sequence between each byte transferred. Instead, multi-byte firmware accesses should issue a single SYNC sequence following the transfer of the multi-byte data phase




Revision Changes Path
1.3 wb_lpc/rtl/verilog/wb_lpc_host.v

http://www.opencores.org/cvsweb.shtml/wb_lpc/rtl/verilog/wb_lpc_host.v.diff?r1=1.2&r2=1.3

(In the diff below, changes in quantity of whitespace are not shown.)

Index: wb_lpc_host.v
===================================================================
RCS file: /cvsroot/hharte/wb_lpc/rtl/verilog/wb_lpc_host.v,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -b -r1.2 -r1.3
--- wb_lpc_host.v 5 Mar 2008 05:50:25 -0000 1.2
+++ wb_lpc_host.v 22 Jul 2008 13:46:42 -0000 1.3
@@ -1,6 +1,6 @@
//////////////////////////////////////////////////////////////////////
//// ////
-//// $Id: wb_lpc_host.v,v 1.2 2008/03/05 05:50:25 hharte Exp $ ////
+//// $Id: wb_lpc_host.v,v 1.3 2008/07/22 13:46:42 hharte Exp $ ////
//// wb_lpc_host.v - Wishbone Slave to LPC Host Bridge ////
//// ////
//// This file is part of the Wishbone LPC Bridge project ////
@@ -165,7 +165,7 @@

// The LPC Bus Address is sent across the bus a nibble at a time;
// however, the most significant nibble is sent first. For firmware and
- // memory cycles, the address is 32-bits. Actually, for memeory accesses,
+ // memory cycles, the address is 32-bits. Actually, for firmware accesses,
// the most significant nibble is known as the IDSEL field. For I/O,
// the address is only 16-bits wide.
case(adr_cnt)
@@ -271,6 +271,9 @@

if(nibble_cnt == 1'b1) // end of byte
begin
+ if((fw_xfr) && (byte_cnt != xfr_len-1)) // Firmware transfer does not have TAR between bytes.
+ state <= `LPC_ST_H_DATA;
+ else
state <= `LPC_ST_H_TAR1;
end
else
@@ -328,8 +331,12 @@
if(nibble_cnt == 1'b1) // Byte transfer complete
if (byte_cnt == xfr_len-1) // End of data transfer phase
state <= `LPC_ST_P_TAR1;
+ else begin
+ if(fw_xfr) // Firmware transfer does not have TAR between bytes.
+ state <= `LPC_ST_P_DATA;
else
state <= `LPC_ST_SYNC;
+ end
else // Go to next nibble
state <= `LPC_ST_P_DATA;
end



1.3 wb_lpc/rtl/verilog/wb_lpc_periph.v

http://www.opencores.org/cvsweb.shtml/wb_lpc/rtl/verilog/wb_lpc_periph.v.diff?r1=1.2&r2=1.3

(In the diff below, changes in quantity of whitespace are not shown.)

Index: wb_lpc_periph.v
===================================================================
RCS file: /cvsroot/hharte/wb_lpc/rtl/verilog/wb_lpc_periph.v,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -b -r1.2 -r1.3
--- wb_lpc_periph.v 5 Mar 2008 05:50:59 -0000 1.2
+++ wb_lpc_periph.v 22 Jul 2008 13:46:42 -0000 1.3
@@ -1,6 +1,6 @@
//////////////////////////////////////////////////////////////////////
//// ////
-//// $Id: wb_lpc_periph.v,v 1.2 2008/03/05 05:50:59 hharte Exp $ ////
+//// $Id: wb_lpc_periph.v,v 1.3 2008/07/22 13:46:42 hharte Exp $ ////
//// wb_lpc_periph.v - LPC Peripheral to Wishbone Master Bridge ////
//// ////
//// This file is part of the Wishbone LPC Bridge project ////
@@ -285,6 +285,9 @@

if(nibble_cnt == 1'b1) // end of byte
begin
+ if((fw_xfr) && (byte_cnt != xfr_len-1)) // Firmware transfer does not have TAR between bytes.
+ state <= `LPC_ST_H_DATA;
+ else
state <= `LPC_ST_H_TAR1;
end
else
@@ -365,8 +368,12 @@
if(nibble_cnt == 1'b1) // Byte transfer complete if (byte_cnt == xfr_len-1) // Byte transfer complete state <= `LPC_ST_P_TAR1; + else begin + if(fw_xfr) // Firmware transfer does not have TAR between bytes. + state <= `LPC_ST_P_DATA; else state <= `LPC_ST_SYNC; + end else state <= `LPC_ST_P_DATA;