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Message
From: cvs at opencores.org<cvs@o...>
Date: Mon Jun 30 18:02:15 CEST 2008
Subject: [cvs-checkins] MODIFIED: cryptosorter ...
Date: 00/08/06 30:18:02 Added: cryptosorter/memocodeDesignContest2008/xup/Sort
SortTester.bsv sorttester.v
Log:
Initial checkin with actual source
Revision Changes Path
1.1 cryptosorter/memocodeDesignContest2008/xup/Sort/SortTester.bsv
http://www.opencores.org/cvsweb.shtml/cryptosorter/memocodeDesignContest2008/xup/Sort/SortTester.bsv?rev=1.1&content-type=text/x-cvsweb-markup
Index: SortTester.bsv
===================================================================
/*
Copyright (c) 2008 MIT
Permission is hereby granted, free of charge, to any person
obtaining a copy of this software and associated documentation
files (the "Software"), to deal in the Software without
restriction, including without limitation the rights to use,
copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following
conditions:
The above copyright notice and this permission notice shall be
included in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
OTHER DEALINGS IN THE SOFTWARE.
Author: Kermin Fleming
*/
import PLBMasterWires::*;
import BRAMInitiatorWires::*;
import PLBMaster::*;
import BRAMFeeder::*;
import Interfaces::*;
import Parameters::*;
import FIFO::*;
import FIFOF::*;
import BRAMFIFO::*;
import GetPut::*;
import Types::*;
import Memocode08Types::*;
import Sort::*;
import SortTree64::*;
import Vector::*;
interface SortTester;
interface PLBMasterWires plbMasterWires;
interface BRAMInitiatorWires#(Bit#(14)) bramInitiatorWires;
endinterface
typedef enum{
Idle,
Running,
Inputing,
Outputing
} TesterState deriving (Bits,Eq);
module mkSortTester (SortTester);
Feeder feeder <- mkBRAMFeeder();
PLBMaster plbMaster <- mkPLBMaster;
Reg#(TesterState) state <- mkReg(Idle);
Reg#(BlockAddr) baseRegStore <- mkRegU();
Reg#(Bit#(64)) timer <- mkRegU();
Reg#(Bit#(20)) resCount <- mkRegU();
Reg#(Bit#(20)) writeCount <- mkRegU();
Reg#(Bool) eos <- mkRegU();
FIFO#(Bit#(20)) resQ <- mkFIFO();
FIFOF#(Maybe#(Record)) writeQ <- mkSizedFIFOF(8);
let sortTree <- mkSortTree64();
let tok_info = sortTree.inStream.getTokInfo();
rule grab_instruction(state == Idle);
PPCMessage inst <- feeder.ppcMessageOutput.get;
Bit#(5) size = truncate(pack(inst));
baseRegStore <= 0;
timer <= 0;
resCount <= (1<<size)<<1;
writeCount <= 1<<size; // half res are for eos
state <= Running;
eos <= False;
endrule
rule read_reserve (state == Running &&
resCount > 0 &&
tok_info[resCount[5:0]] > 0);
resQ.enq(resCount);
resCount <= resCount - 1;
endrule
rule read_request (True);
Bit#(20) val = resQ.first();
Bit#(6) idx = truncate(val);
resQ.deq();
sortTree.inStream.putDeqTok(idx,1);
if (idx == 1)
eos <= !eos;
if (!eos) // enq data
sortTree.inStream.putRecord(idx,tagged Valid zeroExtend({val[19:7],val[5:0]}));
else // eos
sortTree.inStream.putRecord(idx,tagged Invalid);
endrule
rule sync_out_stream (state == Running);
Vector#(1,Bit#(5)) tok = replicate(zeroExtend(pack(writeQ.notFull())));
sortTree.outStream.putTokInfo(tok);
endrule
rule drain_sorter_finish (True);
match {.*,.data} = sortTree.outStream.getRecord();
writeQ.enq(data);
endrule
rule write_to_mem (True);
writeQ.deq();
if (isValid(writeQ.first()))
begin
let data = fromMaybe(?,writeQ.first());
writeCount <= writeCount - 1;
plbMaster.wordInput.put(data);
if (writeCount[1:0] == 1)
begin
baseRegStore <= baseRegStore + fromInteger(valueof(BlockSize));
plbMaster.plbMasterCommandInput.put(tagged StorePage (baseRegStore));
end
end
endrule
rule incrTimer (state == Running);
timer <= timer + 1;
endrule
rule finishSort(state == Running && resCount == 0 && writeCount == 0);
state <= Idle;
feeder.ppcMessageInput.put(truncate(timer));
endrule
rule heart_beat(state == Running && timer[19:0] == 1000000);
feeder.ppcMessageInput.put(0);
endrule
interface plbMasterWires = plbMaster.plbMasterWires;
interface bramInitiatorWires = feeder.bramInitiatorWires;
endmodule
1.1 cryptosorter/memocodeDesignContest2008/xup/Sort/sorttester.v
http://www.opencores.org/cvsweb.shtml/cryptosorter/memocodeDesignContest2008/xup/Sort/sorttester.v?rev=1.1&content-type=text/x-cvsweb-markup
Index: sorttester.v
===================================================================
/*
Copyright (c) 2007 MIT
Permission is hereby granted, free of charge, to any person
obtaining a copy of this software and associated documentation
files (the "Software"), to deal in the Software without
restriction, including without limitation the rights to use,
copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following
conditions:
The above copyright notice and this permission notice shall be
included in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
OTHER DEALINGS IN THE SOFTWARE.
Author: Nirav Dave
*/
module sorttester(CLK,
RST,
plbMasterWires_mABus,
plbMasterWires_mBE,
plbMasterWires_mRNW,
plbMasterWires_mAbort,
plbMasterWires_mBusLock,
plbMasterWires_mCompress,
plbMasterWires_mGuarded,
plbMasterWires_mLockErr,
plbMasterWires_mMSize,
plbMasterWires_mOrdered,
plbMasterWires_mPriority,
plbMasterWires_mRdBurst,
plbMasterWires_mRequest,
plbMasterWires_mSize,
plbMasterWires_mType,
plbMasterWires_mWrBurst,
plbMasterWires_mWrDBus,
plbMasterWires_mRst,
plbMasterWires_mAddrAck,
plbMasterWires_mBusy,
plbMasterWires_mErr,
plbMasterWires_mRdBTerm,
plbMasterWires_mRdDAck,
plbMasterWires_mRdDBus,
plbMasterWires_mRdWdAddr,
plbMasterWires_mRearbitrate,
plbMasterWires_mWrBTerm,
plbMasterWires_mWrDAck,
plbMasterWires_mSSize,
plbMasterWires_sMErr,
plbMasterWires_sMBusy,
bramInitiatorWires_bramRST,
bramInitiatorWires_bramAddr,
bramInitiatorWires_bramDout,
bramInitiatorWires_bramWEN,
bramInitiatorWires_bramEN,
bramInitiatorWires_bramCLK,
bramInitiatorWires_bramDin);
input CLK;
input RST;
// value method plbMasterWires_mABus
output [31 : 0] plbMasterWires_mABus;
// value method plbMasterWires_mBE
output [7 : 0] plbMasterWires_mBE;
// value method plbMasterWires_mRNW
output plbMasterWires_mRNW;
// value method plbMasterWires_mAbort
output plbMasterWires_mAbort;
// value method plbMasterWires_mBusLock
output plbMasterWires_mBusLock;
// value method plbMasterWires_mCompress
output plbMasterWires_mCompress;
// value method plbMasterWires_mGuarded
output plbMasterWires_mGuarded;
// value method plbMasterWires_mLockErr
output plbMasterWires_mLockErr;
// value method plbMasterWires_mMSize
output [1 : 0] plbMasterWires_mMSize;
// value method plbMasterWires_mOrdered
output plbMasterWires_mOrdered;
// value method plbMasterWires_mPriority
output [1 : 0] plbMasterWires_mPriority;
// value method plbMasterWires_mRdBurst
output plbMasterWires_mRdBurst;
// value method plbMasterWires_mRequest
output plbMasterWires_mRequest;
// value method plbMasterWires_mSize
output [3 : 0] plbMasterWires_mSize;
// value method plbMasterWires_mType
output [2 : 0] plbMasterWires_mType;
// value method plbMasterWires_mWrBurst
output plbMasterWires_mWrBurst;
// value method plbMasterWires_mWrDBus
output [63 : 0] plbMasterWires_mWrDBus;
// action method plbMasterWires_plbIN
input plbMasterWires_mRst;
input plbMasterWires_mAddrAck;
input plbMasterWires_mBusy;
input plbMasterWires_mErr;
input plbMasterWires_mRdBTerm;
input plbMasterWires_mRdDAck;
input [63 : 0] plbMasterWires_mRdDBus;
input [2 : 0] plbMasterWires_mRdWdAddr;
input plbMasterWires_mRearbitrate;
input plbMasterWires_mWrBTerm;
input plbMasterWires_mWrDAck;
input plbMasterWires_mSSize;
input plbMasterWires_sMErr;
input plbMasterWires_sMBusy;
// action method bramTargetWires_bramIN
output [31 : 0] bramInitiatorWires_bramAddr;
output [31 : 0] bramInitiatorWires_bramDout;
output [3 : 0] bramInitiatorWires_bramWEN;
output bramInitiatorWires_bramEN;
output bramInitiatorWires_bramCLK;
output bramInitiatorWires_bramRST;
// value method bramTargetWires_bramOUT
input [31 : 0] bramInitiatorWires_bramDin;
wire [13:0] bramInitiatorWires_bramAddr_our;
assign bramInitiatorWires_bramAddr = {16'h00000,bramInitiatorWires_bramAddr_our, 2'b00};
// signals for module outputs
wire [31 : 0] bramTargetWires_dinBRAM,plbMasterWires_mABus;
wire [63 : 0] plbMasterWires_mWrDBus;
wire [7 : 0] plbMasterWires_mBE;
wire [3 : 0] plbMasterWires_mSize;
wire [2 : 0] plbMasterWires_mType;
wire [1 : 0] plbMasterWires_mMSize, plbMasterWires_mPriority;
wire plbMasterWires_mAbort,
plbMasterWires_mBusLock,
plbMasterWires_mCompress,
plbMasterWires_mGuarded,
plbMasterWires_mLockErr,
plbMasterWires_mOrdered,
plbMasterWires_mRNW,
plbMasterWires_mRdBurst,
plbMasterWires_mRequest,
plbMasterWires_mWrBurst;
wire RST_N;
assign RST_N = ~RST;
mkSortTester m(
.CLK(CLK),
.RST_N(RST_N),
.plbMasterWires_mABus(plbMasterWires_mABus),
.plbMasterWires_mBE(plbMasterWires_mBE),
.plbMasterWires_mRNW(plbMasterWires_mRNW),
.plbMasterWires_mAbort(plbMasterWires_mAbort),
.plbMasterWires_mBusLock(plbMasterWires_mBusLock),
.plbMasterWires_mCompress(plbMasterWires_mCompress),
.plbMasterWires_mGuarded(plbMasterWires_mGuarded),
.plbMasterWires_mLockErr(plbMasterWires_mLockErr),
.plbMasterWires_mMSize(plbMasterWires_mMSize),
.plbMasterWires_mOrdered(plbMasterWires_mOrdered),
.plbMasterWires_mPriority(plbMasterWires_mPriority),
.plbMasterWires_mRdBurst(plbMasterWires_mRdBurst),
.plbMasterWires_mRequest(plbMasterWires_mRequest),
.plbMasterWires_mSize(plbMasterWires_mSize),
.plbMasterWires_mType(plbMasterWires_mType),
.plbMasterWires_mWrBurst(plbMasterWires_mWrBurst),
.plbMasterWires_mWrDBus(plbMasterWires_mWrDBus),
.plbMasterWires_mRst(plbMasterWires_mRst),
.plbMasterWires_mAddrAck(plbMasterWires_mAddrAck),
.plbMasterWires_mBusy(plbMasterWires_mBusy),
.plbMasterWires_mErr(plbMasterWires_mErr),
.plbMasterWires_mRdBTerm(plbMasterWires_mRdBTerm),
.plbMasterWires_mRdDAck(plbMasterWires_mRdDAck),
.plbMasterWires_mRdDBus(plbMasterWires_mRdDBus),
.plbMasterWires_mRdWdAddr(plbMasterWires_mRdWdAddr),
.plbMasterWires_mRearbitrate(plbMasterWires_mRearbitrate),
.plbMasterWires_mWrBTerm(plbMasterWires_mWrBTerm),
.plbMasterWires_mWrDAck(plbMasterWires_mWrDAck),
.plbMasterWires_mSSize(plbMasterWires_mSSize),
.plbMasterWires_sMErr(plbMasterWires_sMErr),
.plbMasterWires_sMBusy(plbMasterWires_sMBusy),
.bramInitiatorWires_bramAddr(bramInitiatorWires_bramAddr_our),
.bramInitiatorWires_bramDout(bramInitiatorWires_bramDout),
.bramInitiatorWires_bramWEN(bramInitiatorWires_bramWEN),
.bramInitiatorWires_bramEN(bramInitiatorWires_bramEN),
.bramInitiatorWires_bramCLK(bramInitiatorWires_bramCLK),
.bramInitiatorWires_bramRST(bramInitiatorWires_bramRST),
.bramInitiatorWires_din(bramInitiatorWires_bramDin)
);
endmodule
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