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Message
From: cvs at opencores.org<cvs@o...>
Date: Mon Jun 30 18:02:10 CEST 2008
Subject: [cvs-checkins] MODIFIED: cryptosorter ...
Date: 00/08/06 30:18:02 Added: cryptosorter/memocodeDesignContest2008/sort/BRAM_v BRAM.bsv
BRAMFIFO.bsv BRAMFIFOF.v NewBRAMFIFO.bsv UGBRAM.v
Log:
Initial checkin with actual source
Revision Changes Path
1.1 cryptosorter/memocodeDesignContest2008/sort/BRAM_v/BRAM.bsv
http://www.opencores.org/cvsweb.shtml/cryptosorter/memocodeDesignContest2008/sort/BRAM_v/BRAM.bsv?rev=1.1&content-type=text/x-cvsweb-markup
Index: BRAM.bsv
===================================================================
//----------------------------------------------------------------------//
// The MIT License
//
// Copyright (c) 2008 Alfred Man Cheuk Ng, mcn02@m...
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
//----------------------------------------------------------------------//
// import standard library
import FIFOF::*;
import RWire::*;
//////////////////////////////////////////////////////////////////////////
// unguarded bram interface
interface UGBRAM#(type idx_type, type data_type);
(* always_ready *) method Action read_req(idx_type idx);
method data_type read_resp();
(* always_ready *) method Action write(idx_type idx, data_type data);
endinterface
//////////////////////////////////////////////////////////////////////////
// guarded bram interface
interface BRAM#(type idx_type, type data_type);
method Action read_req(idx_type idx);
method ActionValue#(data_type) read_resp();
method Action write(idx_type idx, data_type data);
endinterface
//////////////////////////////////////////////////////////////////////////
// unguarded bram implementations
// the ugbram verilog suggest a bypass one already
import "BVI" UGBRAM = module mkUGBRAM#(Integer low, Integer high)
(UGBRAM#(idx_type, data_type))
provisos
(Bits#(idx_type, idx),
Bits#(data_type, data),
Literal#(idx_type));
default_clock clk(CLK);
default_reset rst(RST_N);
parameter addr_width = valueOf(idx);
parameter data_width = valueOf(data);
parameter lo = low;
parameter hi = high;
method read_req(READ_A_ADDR) enable(READ_A_ADDR_EN);
method READ_A_DATA read_resp() ready(READ_A_DATA_RDY);
method write(WRITE_B_ADDR, WRITE_B_DATA) enable(WRITE_B_EN);
schedule read_req CF (read_resp, write);
schedule read_req C read_req;
schedule read_resp CF (read_req, write);
schedule read_resp CF read_resp;
schedule write CF (read_req, read_resp);
schedule write C write;
endmodule
module mkUGBRAM_Full(UGBRAM#(idx_type, data_type))
provisos
(Bits#(idx_type, idx),
Bits#(data_type, data),
Literal#(idx_type));
UGBRAM#(idx_type, data_type) bram <- mkUGBRAM(0, valueOf(TExp#(idx)) - 1);
return bram;
endmodule
// bypassUGBRAM = if write req and read req to the same addr, read the new data
module mkBypassUGBRAM_Full
//interface:
(UGBRAM#(idx_type, data_type))
provisos
(Bits#(idx_type, idx),
Bits#(data_type, data),
Literal#(idx_type),
Eq#(idx_type));
UGBRAM#(idx_type, data_type) bram <- mkUGBRAM(0, valueOf(TExp#(idx)) - 1);
return bram;
// Reg#(Maybe#(data_type)) resp <- mkReg(tagged Invalid);
// UGBRAM#(idx_type, data_type) br <- mkUGBRAM_Full;
// RWire#(idx_type) wr_addr <- mkRWire;
// RWire#(data_type) wr_data <- mkRWire;
// RWire#(idx_type) rd_addr <- mkRWire;
// rule checkBypass(True);
// if (isValid(wr_addr.wget) &&
// isValid(rd_addr.wget) &&
// fromMaybe(?,wr_addr.wget) == fromMaybe(?,rd_addr.wget))
// resp <= wr_data.wget;
// else
// resp <= tagged Invalid;
// $display("%m checkBypass write_en: %d, write_addr: %d, write_data: %d, read_en: %d, read_addr: %d, bypass: %d",
// isValid(wr_addr.wget), fromMaybe(?,wr_addr.wget), wr_data.wget,
// isValid(rd_addr.wget), fromMaybe(?,rd_addr.wget),
// fromMaybe(?,wr_addr.wget) == fromMaybe(?,rd_addr.wget));
// endrule
// rule checkReadResp(True);
// let br_resp = br.read_resp;
// let res = fromMaybe(br_resp,resp);
// $display("%m bram resp: %d, resp: %d, actual resp: %d",br_resp,resp,res);
// endrule
// method Action read_req(idx_type idx);
// br.read_req(idx);
// rd_addr.wset(idx);
// endmethod
// method data_type read_resp();
// let br_resp = br.read_resp;
// let res = fromMaybe(br_resp,resp);
// return res;
// endmethod
// method Action write(idx_type idx, data_type data);
// br.write(idx,data);
// wr_addr.wset(idx);
// wr_data.wset(data);
// endmethod
endmodule
//////////////////////////////////////////////////////////////////////////
// guarded bram implementations
// there is no point to make bypassBRAM if it is guarded because
// the BRAM is assumed to have unknown latency
module mkBRAM#(Integer low, Integer high)
(BRAM#(idx_type,data_type))
provisos (Bits#(idx_type, idx),
Bits#(data_type, data),
Literal#(idx_type));
UGBRAM#(idx_type,data_type) ugbram <- mkUGBRAM(low,high);
FIFOF#(data_type) rdataQ <- mkSizedFIFOF(2);
rule getResp(True);
let resp = ugbram.read_resp;
rdataQ.enq(resp);
endrule
method Action read_req(idx_type addr) if (rdataQ.notFull);
ugbram.read_req(addr);
endmethod
method ActionValue#(data_type) read_resp();
rdataQ.deq;
return rdataQ.first;
endmethod
method Action write(idx_type addr, data_type data);
ugbram.write(addr,data);
endmethod
endmodule
1.1 cryptosorter/memocodeDesignContest2008/sort/BRAM_v/BRAMFIFO.bsv
http://www.opencores.org/cvsweb.shtml/cryptosorter/memocodeDesignContest2008/sort/BRAM_v/BRAMFIFO.bsv?rev=1.1&content-type=text/x-cvsweb-markup
Index: BRAMFIFO.bsv
===================================================================
//----------------------------------------------------------------------//
// The MIT License
//
// Copyright (c) 2008 Alfred Man Cheuk Ng, mcn02@m...
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
//----------------------------------------------------------------------//
import FIFO::*;
import FIFOF::*;
import FIFOF_::*;
/***
*
* This module serves as a simple bluespec wrapper for
* the verilog based BRAMFIFO. The imported methods support
* the standard FIFOF and FIFO classes. It should be noted that
* the underlying verilog implementation is gaurded.
*
***/
module mkBRAMFIFO#(Integer count) (FIFO#(fifo_type))
provisos
(Bits#(fifo_type, fifo_size));
FIFOF#(fifo_type) fifo <- mkBRAMFIFOF(count);
method Action enq(fifo_type data);
fifo.enq(data);
endmethod
method Action deq();
fifo.deq();
endmethod
method fifo_type first();
return fifo.first();
endmethod
method Action clear();
fifo.clear();
endmethod
endmodule
module mkBRAMFIFOF#(Integer count) (FIFOF#(fifo_type))
provisos
(Bits#(fifo_type, fifo_size));
FIFOF_#(fifo_type) fifo <- mkBRAMFIFOF_(count);
method Action enq(fifo_type data) if(fifo.i_notFull);
fifo.enq(data);
endmethod
method Action deq() if(fifo.i_notEmpty);
fifo.deq();
endmethod
method fifo_type first() if(fifo.i_notEmpty);
return fifo.first();
endmethod
method Bool notFull;
return fifo.notFull;
endmethod
method Bool notEmpty;
return fifo.notEmpty;
endmethod
method Action clear();
fifo.clear();
endmethod
endmodule
import "BVI" BRAMFIFOF = module mkBRAMFIFOF_#(Integer count)
//interface:
(FIFOF_#(fifo_type))
provisos
(Bits#(fifo_type, fifo_size));
default_clock clk(CLK);
parameter log_data_count = log2(count);
parameter data_count = count;
parameter data_width = valueOf(fifo_size);
method enq((* reg *)D_IN) enable(ENQ);
method deq() enable(DEQ);
method (* reg *)D_OUT first;
method FULL_N notFull;
method FULL_N i_notFull;
method (* reg *)EMPTY_N notEmpty;
method (* reg *)EMPTY_N i_notEmpty;
method clear() enable(CLR);
schedule deq CF (enq, i_notEmpty, i_notFull) ;
schedule enq CF (deq, first, i_notEmpty, i_notFull) ;
schedule (first, notEmpty, notFull) CF
(first, i_notEmpty, i_notFull, notEmpty, notFull) ;
schedule (i_notEmpty, i_notFull) CF
(clear, first, i_notEmpty, i_notFull, notEmpty, notFull) ;
schedule (clear, deq, enq) SBR clear ;
schedule first SB (clear, deq) ;
schedule (notEmpty, notFull) SB (clear, deq, enq) ;
/*schedule first SB (deq,enq,clear);
schedule first CF (first,notFull,notEmpty);
schedule notFull SB (deq,enq,clear);
schedule notFull CF (first,notFull,notEmpty);
schedule notEmpty SB (deq,enq,clear);
schedule notEmpty CF (first,notFull,notEmpty);
schedule deq CF enq;
schedule deq SB clear;
schedule deq C deq;
schedule enq CF deq;
schedule enq SB clear;
schedule enq C enq;
schedule clear C clear;*/
endmodule
1.1 cryptosorter/memocodeDesignContest2008/sort/BRAM_v/BRAMFIFOF.v
http://www.opencores.org/cvsweb.shtml/cryptosorter/memocodeDesignContest2008/sort/BRAM_v/BRAMFIFOF.v?rev=1.1&content-type=text/x-cvsweb-markup
Index: BRAMFIFOF.v
===================================================================
//----------------------------------------------------------------------//
// The MIT License
//
// Copyright (c) 2008 Alfred Man Cheuk Ng, mcn02@m...
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
//----------------------------------------------------------------------//
/***
*
* This module implements a parametric verilog sized fifo. This particular
* sized fifo will synthesize on to Xilinx block rams. The fifo is parametric
* in terms of both data width and the number of data stored in the fifo.
* the interface is gaurded. The fifo is not loopy.
* The methods supported by the FIFO are clear, dequeue, enqueue, notFull,
* and notEmpty
*
***/
module BRAMFIFOF(CLK, RST_N,
D_IN, CLR, DEQ,
ENQ, D_OUT, FULL_N, EMPTY_N);
// synopsys template
parameter log_data_count = 0;
parameter data_count = 1;
parameter data_width = 1;
input CLK;
input RST_N;
input [data_width - 1 : 0] D_IN;
input CLR;
input DEQ;
input ENQ;
output [data_width - 1 : 0] D_OUT;
output FULL_N;
output EMPTY_N;
reg [data_width - 1 : 0] arr[0:data_count]; /*synthesis syn_ramstyle = "block_ram"*/
reg skid_flag;
reg [log_data_count + 2 : 0] fifo_data_count;
reg [log_data_count + 2 : 0] read_ptr;
reg [log_data_count + 2 : 0] read_ptr_current;
reg [log_data_count + 2 : 0] write_ptr;
reg [data_width - 1 : 0] skid_buffer; // this is a fast output buffer
reg [data_width - 1 : 0] RAM_OUT;
assign D_OUT = (skid_flag)?skid_buffer:RAM_OUT;
assign FULL_N = !(fifo_data_count == data_count);
assign EMPTY_N = !(fifo_data_count == 0);
integer x;
always@(*)
begin
if(DEQ)
begin
read_ptr_current = (read_ptr == data_count)?0:(read_ptr + 1);
end
else
begin
read_ptr_current = read_ptr;
end
end
always@(posedge CLK)
begin
if (!RST_N)
begin //Make simulation behavior consistent with Xilinx synthesis
// synopsys translate_off
for (x = 0; x < data_count + 1; x = x + 1)
begin
arr[x] <= 0;
end
// synopsys translate_on
fifo_data_count <= 0;
skid_buffer <= 0;
skid_flag <= 0;
read_ptr <= 0;
write_ptr <= 0;
//$display("Params: data_count: %d, log_data_count: %d, data_width: %d", data_count, log_data_count, data_width);
end
else
begin
// assign output buffer
skid_buffer <= D_IN;
if(CLR)
begin
skid_flag <= 0;
end
else if(ENQ && ((fifo_data_count == 0) || ((fifo_data_count == 1) && DEQ)))
begin
//$display("Enque to output buffer");
skid_flag <= 1;
end
else
begin
skid_flag <= 0;
end
// write_ptr
if(CLR)
begin
write_ptr <= 0;
end
else if(ENQ)
begin
//$display("Enque to BRAM[%d]: %d", write_ptr,D_IN);
write_ptr <= (write_ptr == data_count)?0:(write_ptr + 1);
end
else
begin
write_ptr <= write_ptr;
end
//read_ptr
if(CLR)
begin
read_ptr <= 0;
end
else if(DEQ)
begin
//$display("Advancing read ptr");
read_ptr <= (read_ptr == data_count)?0:(read_ptr + 1);
end
else
begin
read_ptr <= read_ptr;
end
// assign fifo data_count
if(CLR)
begin
fifo_data_count <= 0;
end
else if(ENQ && DEQ)
begin
fifo_data_count <= fifo_data_count;
end
else if(ENQ)
begin
fifo_data_count <= fifo_data_count + 1;
end
else if(DEQ)
begin
fifo_data_count <= fifo_data_count - 1;
end
else
begin
fifo_data_count <= fifo_data_count;
end
if(ENQ)
begin
arr[write_ptr] <= D_IN;
end
RAM_OUT <= arr[read_ptr_current];
end
end // always@ (posedge CLK)
endmodule
1.1 cryptosorter/memocodeDesignContest2008/sort/BRAM_v/NewBRAMFIFO.bsv
http://www.opencores.org/cvsweb.shtml/cryptosorter/memocodeDesignContest2008/sort/BRAM_v/NewBRAMFIFO.bsv?rev=1.1&content-type=text/x-cvsweb-markup
Index: NewBRAMFIFO.bsv
===================================================================
//----------------------------------------------------------------------//
// Qualcomm Proprietary //
// Copyright (c) 2006 Qualcomm Inc. //
// All rights reserved. //
//----------------------------------------------------------------------//
// File: $RCSfile: NewBRAMFIFO.bsv,v $
// Author: Alfred Man Cheuk Ng, Abhinav Agarwal
// Created: 2007-07-13
// Description: FIFO and FIFOF implemented using BRAM, default 4 elements
//
//----------------------------------------------------------------------//
// $Id: NewBRAMFIFO.bsv,v 1.1 2008/06/30 16:02:10 kfleming Exp $
//----------------------------------------------------------------------//
import BRAM::*;
import EHRReg::*;
import FIFO::*;
import FIFOF::*;
// schedule = (notEmpty = first < deq < notFull < enq) C clear
module mkNewBRAMFIFOF(FIFOF#(a))
provisos (Bits#(a,asz));
// state elements
UGBRAM#(Bit#(8), a) bram <- mkBypassUGBRAM_Full; // 256 elements memory storage
EHRReg#(2,Bit#(8)) head <- mkEHRReg(0); // head pointer
EHRReg#(2,Bit#(8)) tail <- mkEHRReg(0); // tail pointer
EHRReg#(2,Bool) over <- mkEHRReg(False); // negate everytime either head or tail overthrow
Wire#(a) resp <- mkDWire(?); //
// signals
let canDeq = head[0] != tail[0] || over[0];
let canEnq = head[0] != tail[0] || !over[0]; // cannot enq and deq simutaneously when full
// rules
rule prefetchHead(True);
bram.read_req(head[1]);
endrule
rule getReadresp(True);
resp <= bram.read_resp;
endrule
// interface methods
method Action enq(a x) if (canEnq);
bram.write(tail[1],x);
if (tail[1] == maxBound) // max idx, wrap around ptr
begin
tail[1] <= 0;
over[1] <= !over[1];
end
else
tail[1] <= tail[1] + 1;
endmethod
method a first() if (canDeq);
return resp;
endmethod
method Action deq() if (canDeq);
if (head[0] == maxBound)
begin
head[0] <= 0;
over[0] <= !over[0];
end
else
head[0] <= head[0] + 1;
endmethod
method Bool notEmpty();
return canDeq;
endmethod
method Bool notFull();
return canEnq;
endmethod
method Action clear();
head[0] <= 0;
tail[1] <= 0;
over[1] <= False;
endmethod
endmodule
// schedule = (first < deq < enq) C clear
module mkNewBRAMFIFO(FIFO#(a))
provisos (Bits#(a,asz));
// state elements
FIFOF#(a) fifo <- mkNewBRAMFIFOF;
// interface methods
method Action enq(a x) = fifo.enq(x);
method a first() = fifo.first;
method Action deq() = fifo.deq;
method Action clear() = fifo.clear;
endmodule
1.1 cryptosorter/memocodeDesignContest2008/sort/BRAM_v/UGBRAM.v
http://www.opencores.org/cvsweb.shtml/cryptosorter/memocodeDesignContest2008/sort/BRAM_v/UGBRAM.v?rev=1.1&content-type=text/x-cvsweb-markup
Index: UGBRAM.v
===================================================================
//----------------------------------------------------------------------//
// The MIT License
//
// Copyright (c) 2008 Alfred Man Cheuk Ng, mcn02@m...
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
//----------------------------------------------------------------------//
// unguarded bram
// When synthesized, one basic BRAM instance = 4096 bits,
// the maximum width = 16, depth = 256
module UGBRAM (CLK,
RST_N,
READ_A_ADDR_EN,
READ_A_ADDR,
READ_A_DATA,
READ_A_DATA_RDY,
WRITE_B_EN,
WRITE_B_ADDR,
WRITE_B_DATA
);
parameter addr_width = 1;
parameter data_width = 1;
parameter lo = 0;
parameter hi = 1;
input CLK;
input RST_N;
// read port
// req, always ready
input READ_A_ADDR_EN;
input [addr_width-1:0] READ_A_ADDR;
// resp
output [data_width-1:0] READ_A_DATA;
output READ_A_DATA_RDY;
// write port, always ready
input WRITE_B_EN;
input [addr_width-1:0] WRITE_B_ADDR;
input [data_width-1:0] WRITE_B_DATA;
reg [addr_width-1:0] READ_ADDR; // read addr need to be registered for block ram to be inferred
reg READ_A_DATA_RDY;
reg [data_width-1:0] RAM [hi:lo]; /*synthesis syn_ramstyle = "block_ram"*/
assign READ_A_DATA = RAM[READ_ADDR];
always@(posedge CLK)
begin
if (!RST_N)
READ_A_DATA_RDY <= 0;
else
begin
if(WRITE_B_EN)
RAM[WRITE_B_ADDR] <= WRITE_B_DATA;
READ_ADDR <= READ_A_ADDR;
READ_A_DATA_RDY <= (READ_A_ADDR_EN) ? 1 : 0;
end
end // always@ (posedge CLK)
endmodule
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