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Message
From: cvs at opencores.org<cvs@o...>
Date: Mon Jun 30 18:02:06 CEST 2008
Subject: [cvs-checkins] MODIFIED: cryptosorter ...
Date: 00/08/06 30:18:02 Added: cryptosorter/memocodeDesignContest2008/sort
BRAMLevel1Merger.bsv BRAMLevel2Merger.bsv
BRAMLevel3Merger.bsv BRAMLevel4Merger.bsv
BRAMLevel5Merger.bsv BRAMLevel6Merger.bsv
BRAMLevel7Merger.bsv BRAMLevel8Merger.bsv
EHRReg.bsv Level1Merger.bsv Makefile Sort.bsv
SortTree128.bsv SortTree16.bsv SortTree256.bsv
SortTree64.bsv SortTreeTestbench.bsv
SynthRegFiles.bsv VLevelFIFO.bsv
VLevelFIFOTester.bsv
mkBRAMLevel2MergerInstance.sched
mkBRAMLevel3MergerInstance.sched
mkBRAMLevel4MergerInstance.sched
mkBRAMLevel5MergerInstance.sched
mkBRAMLevel6MergerInstance.sched
mkLevel1MergerInstance.sched mkSortTree64.sched
readme
Log:
Initial checkin with actual source
Revision Changes Path
1.1 cryptosorter/memocodeDesignContest2008/sort/BRAMLevel1Merger.bsv
http://www.opencores.org/cvsweb.shtml/cryptosorter/memocodeDesignContest2008/sort/BRAMLevel1Merger.bsv?rev=1.1&content-type=text/x-cvsweb-markup
Index: BRAMLevel1Merger.bsv
===================================================================
//----------------------------------------------------------------------//
// The MIT License
//
// Copyright (c) 2008 Alfred Man Cheuk Ng, mcn02@m...
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
//----------------------------------------------------------------------//
// import standard librarys
import Connectable::*;
import GetPut::*;
import FIFO::*;
import StmtFSM::*;
import Vector::*;
// import self-made library
import BRAMVLevelFIFO::*;
import EHRReg::*;
import VLevelFIFO::*;
import Sort::*;
typedef 4 FIFO_SZ;
typedef TLog#(TAdd#(FIFO_SZ,1)) TOK_SZ;
(* synthesize *)
module mkBRAMLevel1MergerInstance (SortLevel#(2,1,Bit#(TOK_SZ),Bit#(TOK_SZ),Maybe#(Bit#(128))));
Bit#(FIFO_SZ) dntCare = ?;
let res <- mkBRAMOneLevelMerger(dntCare, notValid, fromMaybe(?), mkZeroCycleScheduler);
return res;
endmodule
1.1 cryptosorter/memocodeDesignContest2008/sort/BRAMLevel2Merger.bsv
http://www.opencores.org/cvsweb.shtml/cryptosorter/memocodeDesignContest2008/sort/BRAMLevel2Merger.bsv?rev=1.1&content-type=text/x-cvsweb-markup
Index: BRAMLevel2Merger.bsv
===================================================================
//----------------------------------------------------------------------//
// The MIT License
//
// Copyright (c) 2008 Alfred Man Cheuk Ng, mcn02@m...
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
//----------------------------------------------------------------------//
// import standard librarys
import Connectable::*;
import GetPut::*;
import FIFO::*;
import StmtFSM::*;
import Vector::*;
// import self-made library
import BRAMVLevelFIFO::*;
import EHRReg::*;
import VLevelFIFO::*;
import Sort::*;
typedef 4 FIFO_SZ;
typedef TLog#(TAdd#(FIFO_SZ,1)) TOK_SZ;
(* synthesize *)
module mkBRAMLevel2MergerInstance (SortLevel#(4,2,Bit#(TOK_SZ),Bit#(2),Maybe#(Bit#(128))));
Bit#(FIFO_SZ) dntCare = ?;
let res <- mkBRAMOneLevelMerger(dntCare, notValid, fromMaybe(?), mkZeroCycleScheduler, mkDecrOneBRAMVLevelFIFO);
return res;
endmodule
1.1 cryptosorter/memocodeDesignContest2008/sort/BRAMLevel3Merger.bsv
http://www.opencores.org/cvsweb.shtml/cryptosorter/memocodeDesignContest2008/sort/BRAMLevel3Merger.bsv?rev=1.1&content-type=text/x-cvsweb-markup
Index: BRAMLevel3Merger.bsv
===================================================================
//----------------------------------------------------------------------//
// The MIT License
//
// Copyright (c) 2008 Alfred Man Cheuk Ng, mcn02@m...
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
//----------------------------------------------------------------------//
// import standard librarys
import Connectable::*;
import GetPut::*;
import FIFO::*;
import StmtFSM::*;
import Vector::*;
// import self-made library
import BRAMVLevelFIFO::*;
import EHRReg::*;
import VLevelFIFO::*;
import Sort::*;
typedef 4 FIFO_SZ;
typedef TLog#(TAdd#(FIFO_SZ,1)) TOK_SZ;
(* synthesize *)
module mkBRAMLevel3MergerInstance (SortLevel#(8,4,Bit#(TOK_SZ),Bit#(TOK_SZ),Maybe#(Bit#(128))));
Bit#(FIFO_SZ) dntCare = ?;
let res <- mkBRAMOneLevelMerger(dntCare, notValid, fromMaybe(?), mkZeroCycleScheduler, mkDecrOneBRAMVLevelFIFO);
return res;
endmodule
1.1 cryptosorter/memocodeDesignContest2008/sort/BRAMLevel4Merger.bsv
http://www.opencores.org/cvsweb.shtml/cryptosorter/memocodeDesignContest2008/sort/BRAMLevel4Merger.bsv?rev=1.1&content-type=text/x-cvsweb-markup
Index: BRAMLevel4Merger.bsv
===================================================================
//----------------------------------------------------------------------//
// The MIT License
//
// Copyright (c) 2008 Alfred Man Cheuk Ng, mcn02@m...
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
//----------------------------------------------------------------------//
// import standard librarys
import Connectable::*;
import GetPut::*;
import FIFO::*;
import StmtFSM::*;
import Vector::*;
// import self-made library
import BRAMVLevelFIFO::*;
import EHRReg::*;
import VLevelFIFO::*;
import Sort::*;
typedef 4 FIFO_SZ;
typedef TLog#(TAdd#(FIFO_SZ,1)) TOK_SZ;
(* synthesize *)
module mkBRAMLevel4MergerInstance (SortLevel#(16,8,Bit#(TOK_SZ),Bit#(TOK_SZ),Maybe#(Bit#(128))));
Bit#(FIFO_SZ) dntCare = ?;
let res <- mkBRAMOneLevelMerger(dntCare, notValid, fromMaybe(?), mkZeroCycleScheduler, mkBRAMVLevelFIFO);
return res;
endmodule
1.1 cryptosorter/memocodeDesignContest2008/sort/BRAMLevel5Merger.bsv
http://www.opencores.org/cvsweb.shtml/cryptosorter/memocodeDesignContest2008/sort/BRAMLevel5Merger.bsv?rev=1.1&content-type=text/x-cvsweb-markup
Index: BRAMLevel5Merger.bsv
===================================================================
//----------------------------------------------------------------------//
// The MIT License
//
// Copyright (c) 2008 Alfred Man Cheuk Ng, mcn02@m...
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
//----------------------------------------------------------------------//
// import standard librarys
import Connectable::*;
import GetPut::*;
import FIFO::*;
import StmtFSM::*;
import Vector::*;
// import self-made library
import BRAMVLevelFIFO::*;
import EHRReg::*;
import VLevelFIFO::*;
import Sort::*;
typedef 4 FIFO_SZ;
typedef TLog#(TAdd#(FIFO_SZ,1)) TOK_SZ;
(* synthesize *)
module mkBRAMLevel5MergerInstance (SortLevel#(32,16,Bit#(TOK_SZ),Bit#(TOK_SZ),Maybe#(Bit#(128))));
Bit#(FIFO_SZ) dntCare = ?;
let res <- mkBRAMOneLevelMerger(dntCare, notValid, fromMaybe(?), mkOneCycleScheduler2, mkDecrOneBRAMVLevelFIFO);
return res;
endmodule
1.1 cryptosorter/memocodeDesignContest2008/sort/BRAMLevel6Merger.bsv
http://www.opencores.org/cvsweb.shtml/cryptosorter/memocodeDesignContest2008/sort/BRAMLevel6Merger.bsv?rev=1.1&content-type=text/x-cvsweb-markup
Index: BRAMLevel6Merger.bsv
===================================================================
//----------------------------------------------------------------------//
// The MIT License
//
// Copyright (c) 2008 Alfred Man Cheuk Ng, mcn02@m...
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
//----------------------------------------------------------------------//
// import standard librarys
import Connectable::*;
import GetPut::*;
import FIFO::*;
import StmtFSM::*;
import Vector::*;
// import self-made library
import BRAMVLevelFIFO::*;
import EHRReg::*;
import VLevelFIFO::*;
import Sort::*;
typedef 16 FIFO_SZ;
typedef TLog#(TAdd#(FIFO_SZ,1)) TOK_SZ;
typedef 4 NEXT_FIFO_SZ;
typedef TLog#(TAdd#(NEXT_FIFO_SZ,1)) NEXT_TOK_SZ;
(* synthesize *)
module mkBRAMLevel6MergerInstance (SortLevel#(64,32,Bit#(TOK_SZ),Bit#(NEXT_TOK_SZ),Maybe#(Bit#(128))));
Bit#(FIFO_SZ) dntCare = ?;
let res <- mkBRAMOneLevelMerger(dntCare, notValid, fromMaybe(?), mkOneCycleScheduler2, mkBRAMVLevelFIFO);
return res;
endmodule
1.1 cryptosorter/memocodeDesignContest2008/sort/BRAMLevel7Merger.bsv
http://www.opencores.org/cvsweb.shtml/cryptosorter/memocodeDesignContest2008/sort/BRAMLevel7Merger.bsv?rev=1.1&content-type=text/x-cvsweb-markup
Index: BRAMLevel7Merger.bsv
===================================================================
//----------------------------------------------------------------------//
// The MIT License
//
// Copyright (c) 2008 Alfred Man Cheuk Ng, mcn02@m...
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
//----------------------------------------------------------------------//
// import standard librarys
import Connectable::*;
import GetPut::*;
import FIFO::*;
import StmtFSM::*;
import Vector::*;
// import self-made library
import BRAMVLevelFIFO::*;
import EHRReg::*;
import VLevelFIFO::*;
import Sort::*;
typedef 16 FIFO_SZ;
typedef TLog#(TAdd#(FIFO_SZ,1)) TOK_SZ;
typedef 16 NEXT_FIFO_SZ;
typedef TLog#(TAdd#(NEXT_FIFO_SZ,1)) NEXT_TOK_SZ;
(* synthesize *)
module mkBRAMLevel7MergerInstance (SortLevel#(128,64,Bit#(TOK_SZ),Bit#(NEXT_TOK_SZ),Maybe#(Bit#(128))));
Bit#(FIFO_SZ) dntCare = ?;
let res <- mkBRAMOneLevelMerger(dntCare, notValid, fromMaybe(?), mkOneCycleScheduler2, mkBRAMVLevelFIFO);
return res;
endmodule
1.1 cryptosorter/memocodeDesignContest2008/sort/BRAMLevel8Merger.bsv
http://www.opencores.org/cvsweb.shtml/cryptosorter/memocodeDesignContest2008/sort/BRAMLevel8Merger.bsv?rev=1.1&content-type=text/x-cvsweb-markup
Index: BRAMLevel8Merger.bsv
===================================================================
//----------------------------------------------------------------------//
// The MIT License
//
// Copyright (c) 2008 Alfred Man Cheuk Ng, mcn02@m...
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
//----------------------------------------------------------------------//
// import standard librarys
import Connectable::*;
import GetPut::*;
import FIFO::*;
import StmtFSM::*;
import Vector::*;
// import self-made library
import BRAMVLevelFIFO::*;
import EHRReg::*;
import VLevelFIFO::*;
import Sort::*;
(* synthesize *)
module mkBRAMLevel8MergerInstance (SortLevel#(256,128,Bit#(5),Bit#(5),Maybe#(Bit#(128))));
let res <- mkBRAMOneLevelMerger(notValid, fromMaybe(?), mkOneCycleScheduler2, mkBRAMVLevelFIFO);
return res;
endmodule
1.1 cryptosorter/memocodeDesignContest2008/sort/EHRReg.bsv
http://www.opencores.org/cvsweb.shtml/cryptosorter/memocodeDesignContest2008/sort/EHRReg.bsv?rev=1.1&content-type=text/x-cvsweb-markup
Index: EHRReg.bsv
===================================================================
//----------------------------------------------------------------------//
// The MIT License
//
// Copyright (c) 2008 Alfred Man Cheuk Ng, mcn02@m...
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
//----------------------------------------------------------------------//
//////////////////////////////////////////////////////////
// Bluespec Library (Not Qualcomm Proprietary)
//
// Interface: EHRReg#(sz, data_t)
// Description: create a EHRReg of data_t with sz read
// and write ports, the scheduling is
// read0 < write0 < read1 < write1 < ....
// Created: Alfred Man Cheuk Ng
//
// Module: mkEHRReg(data_t init)
// Description: create the EHRReg with init as initial value
/////////////////////////////////////////////////////////
import RWire::*;
import Vector::*;
interface VRead#(type a);
method a read();
endinterface
interface EHR#(type a);
interface VRead#(a) vRead;
interface Reg#(a) vReg;
endinterface
typedef Vector#(sz, Reg#(a)) EHRReg#(numeric type sz, type a);
module mkVRead#(Reg#(a) first)
(VRead#(a)) provisos (Bits#(a,asz));
method a read();
return first;
endmethod
endmodule // mkVRead
module mkEHR#(VRead#(a) last)
(EHR#(a)) provisos (Bits#(a,asz));
RWire#(a) rwire <- mkRWire;
interface VRead vRead;
method a read();
let res = (isValid(rwire.wget)) ?
fromMaybe(?,rwire.wget) :
last.read;
return res;
endmethod
endinterface
interface Reg vReg;
method Action _write(a x);
rwire.wset(x);
endmethod
method a _read();
return last.read;
endmethod
endinterface
endmodule
module mkEHRReg#(a init) (EHRReg#(sz,a)) provisos (Bits#(a,asz));
Reg#(a) dataReg <- mkReg(init);
VRead#(a) fstVRead <- mkVRead(dataReg);
Vector#(sz, EHR#(a)) ehrs = newVector;
EHRReg#(sz, a) ehrReg = newVector;
ehrs[0] <- mkEHR(fstVRead);
ehrReg[0] = ehrs[0].vReg;
for(Integer i = 1; i < valueOf(sz); i = i + 1)
begin
ehrs[i] <- mkEHR(ehrs[i-1].vRead);
ehrReg[i] = ehrs[i].vReg;
end
rule updateReg(True);
dataReg <= ehrs[valueOf(sz)-1].vRead.read;
endrule
return ehrReg;
endmodule // mkEHRReg
1.1 cryptosorter/memocodeDesignContest2008/sort/Level1Merger.bsv
http://www.opencores.org/cvsweb.shtml/cryptosorter/memocodeDesignContest2008/sort/Level1Merger.bsv?rev=1.1&content-type=text/x-cvsweb-markup
Index: Level1Merger.bsv
===================================================================
//----------------------------------------------------------------------//
// The MIT License
//
// Copyright (c) 2008 Alfred Man Cheuk Ng, mcn02@m...
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
//----------------------------------------------------------------------//
// import standard librarys
import Connectable::*;
import GetPut::*;
import FIFO::*;
import StmtFSM::*;
import Vector::*;
// import self-made library
import BRAMVLevelFIFO::*;
import EHRReg::*;
import VLevelFIFO::*;
import Sort::*;
(* synthesize *)
module mkLevel1MergerInstance (SortTree#(2,Bit#(2),Maybe#(Bit#(128))));
let res <- mkTwoToOneMerger(notValid, fromMaybe(?));
return res;
endmodule
1.1 cryptosorter/memocodeDesignContest2008/sort/Makefile
http://www.opencores.org/cvsweb.shtml/cryptosorter/memocodeDesignContest2008/sort/Makefile?rev=1.1&content-type=text/x-cvsweb-markup
Index: Makefile
===================================================================
BSC_COMP = bsc
VER_OPTS = +RTS -K100000000 --RTS -u -verilog -elab -no-show-method-conf \
-aggressive-conditions -vdir ./build/vdir -bdir ./build/bdir -dschedule
SIM_OPTS = +RTS -K100000000 --RTS -u -verilog -aggressive-conditions -dschedule -vdir ./build/vdir -bdir ./build/bdir
EXE_OPTS = +RTS -K100000000 --RTS -verilog -vsim iverilog -vdir ./build/vdir -bdir ./build/bdir
SIM_OPTS_NEW = +RTS -K100000000 --RTS -u -sim -aggressive-conditions -dschedule -vdir ./build/vdir -bdir ./build/bdir
sortdir = .
commondir = ../common
bsv_sim = ./BRAM_v
bsv_ver = ./BRAM_v
level_fifo_addr = ./BRAMLevelFIFOAdders
level_fifo_muxes = ./BRAMLevelFIFOMuxes
bram_fifo_testbench:
mkdir -p build
mkdir -p build/bdir
mkdir -p build/vdir
cp $(level_fifo_addr)/zeros.data ./
$(BSC_COMP) $(SIM_OPTS) -show-schedule -p +:$(bsv_sim):./:$(commondir):$(level_fifo_addr):./build/bdir -g mkVLevelFIFOTester $(sortdir)/VLevelFIFOTester.bsv > out.log
$(BSC_COMP) $(EXE_OPTS) -e mkVLevelFIFOTester ./build/vdir/*.v $(bsv_sim)/*.v
bram_fifo_testbench_full:
mkdir -p build
mkdir -p build/bdir
mkdir -p build/vdir
cp $(level_fifo_addr)/zeros.data ./
$(BSC_COMP) $(SIM_OPTS) -show-schedule -p +:./:$(bsv_sim):$(commondir):$(level_fifo_addr):./build/bdir -g mkVLevelFIFOTesterFull $(sortdir)/VLevelFIFOTester.bsv > out.log
$(BSC_COMP) $(EXE_OPTS) -e mkVLevelFIFOTesterFull ./build/vdir/*.v $(bsv_sim)/*.v
sort_tree_perf_testbench:
mkdir -p build
mkdir -p build/bdir
mkdir -p build/vdir
$(BSC_COMP) $(SIM_OPTS) -show-schedule -p +:./:$(commondir):$(bsv_sim):$(level_fifo_addr):./build/bdir -g mkSortTreeTestbench $(sortdir)/SortTreeTestbench.bsv > out.log
$(BSC_COMP) $(EXE_OPTS) -e mkSortTreeTestbench ./build/vdir/*.v $(bsv_sim)/*.v
sort_tree_adder_verilog: clean
mkdir -p build
mkdir -p build/bdir
mkdir -p build/vdir
$(BSC_COMP) $(VER_OPTS) -p +:$(bsv_ver):$(level_fifo_addr):./:$(commondir):./build/bdir -g mkBRAMLevel6MergerInstance $(sortdir)/Sort.bsv > out.log
sort_tree_128_verilog: clean
mkdir -p build
mkdir -p build/bdir
mkdir -p build/vdir
$(BSC_COMP) $(VER_OPTS) -p +:$(bsv_ver):$(level_fifo_addr):./:$(commondir):./build/bdir -g mkSortTree128 $(sortdir)/SortTree128.bsv > out.log
sort_tree_256_verilog: clean
mkdir -p build
mkdir -p build/bdir
mkdir -p build/vdir
$(BSC_COMP) $(VER_OPTS) -p +:$(bsv_ver):$(level_fifo_addr):./:$(commondir):./build/bdir -g mkSortTree256 $(sortdir)/SortTree256.bsv > out.log
sort_tree_mux_verilog: clean
mkdir -p build
mkdir -p build/bdir
mkdir -p build/vdir
$(BSC_COMP) $(VER_OPTS) -p +:$(bsv_ver):./:$(commondir):$(level_fifo_muxes):./build/bdir -g mkBRAMLevel6MergerInstance $(sortdir)/Sort.bsv > out.log
butter_tb:
mkdir -p build
mkdir -p build/bdir
mkdir -p build/vdir
$(BSC_COMP) $(VER_OPTS) -p +:$(bsv_ver):./:$(commondir):$(level_fifo_muxes):./build/bdir -g mkButterflySortTest $(sortdir)/ButterflySort.bsv > out.log
$(BSC_COMP) $(EXE_OPTS) -e mkButterflySortTest ./build/vdir/*.v $(bsv_sim)/*.v
%:
mkdir -p build
mkdir -p build/bdir
mkdir -p build/vdir
$(BSC_COMP) $(VER_OPTS) -show-schedule -p +:$(bsv_sim):$(level_fifo_addr):./:$(commondir):./build/bdir $@.bsv
bram_fifo_test:
mkdir -p build
mkdir -p build/bdir
mkdir -p build/vdir
$(BSC_COMP) $(SIM_OPTS) -show-schedule -p +:./:$(commondir):$(bsv_sim):$(level_fifo_addr):./build/bdir -g mkBRAMFIFOTest $(sortdir)/BRAMFIFOTest.bsv > out.log
$(BSC_COMP) $(EXE_OPTS) -e mkBRAMFIFOTest ./build/vdir/*.v $(bsv_sim)/*.v
sort_tree_test:
mkdir -p build
mkdir -p build/bdir
mkdir -p build/vdir
$(BSC_COMP) $(SIM_OPTS) -show-schedule -p +:./:$(commondir):$(bsv_sim):$(level_fifo_addr):./build/bdir -g mkSortTest $(sortdir)/SortTest.bsv > out.log
$(BSC_COMP) $(EXE_OPTS) -e mkSortTest ./build/vdir/*.v $(bsv_sim)/*.v
.PHONY: clean
clean:
rm -rf build
1.1 cryptosorter/memocodeDesignContest2008/sort/Sort.bsv
http://www.opencores.org/cvsweb.shtml/cryptosorter/memocodeDesignContest2008/sort/Sort.bsv?rev=1.1&content-type=text/x-cvsweb-markup
Index: Sort.bsv
===================================================================
//----------------------------------------------------------------------//
// The MIT License
//
// Copyright (c) 2008 Alfred Man Cheuk Ng, mcn02@m...
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
//----------------------------------------------------------------------//
//////////////////////////////////////////////////////////////////////////
// Summary:
//
// This file describes the implementations of a level of a merge tree, there
// are two implementations: 1) mkTwoToOneMerger and 2) mkBRAMOneLevelMerger.
// "mkTwoToOneMerger" is used to instantiate the top level
// (i.e. the 1st level) of the sort tree. It is a straight forward implementation of
// a two-to-one merger which merges two sorted streams into a single sorted stream.
// The implementation is parameterized for the width of the each data entry.
// "mkBRAMOneLevelMerger" is used to instantiate other levels of the sort tree.
// The implementation merges 2n sorted streams into n sorted streams, whereas n is
// a static parameter. It is obvious that an straight forward implementation
// will simply have n two-to-one mergers. However, this makes the area of one level
// roughly grows twice as big as the previous level. Since the performance of
// is bottlenecked by the top level, we decide to time multiplex a single two-to-one
// merger between the 2n streams. This allows the area of the design grow with the level
// while maintaining roughtly the same performance throughput. One of the biggest challenges
// of the design is to determine which two stream to be merged next.
// The problem gets tougher with lower level of the sort tree because more streams are available.
// To solve this problem, we make the scheduler as a parameter to "mkBRAMOneLevelMerger".
// The scheduler implements the algorithm for picking the next two stream to merge.
// We have different implementations of the scheduler which have different complexity and
// take different number of cycles to return the decision. By passing the appropriate scheduler
// implementations to the same "mkBRAMOneLevelMerger" definition, we can instantiate
// different levels of the sort tree with roughly the same critical path.
//////////////////////////////////////////////////////////////////////////
// import standard librarys
import Connectable::*;
import GetPut::*;
import FIFO::*;
import FIFOF::*;
import StmtFSM::*;
import Vector::*;
// import self-made library
import BRAMVLevelFIFO::*;
import EHRReg::*;
import VLevelFIFO::*;
`define SortDebug0 False
`define SortDebug1 False
//////////////////////////////////////////////////////////////////////////////////////////////
// interfaces definitions
interface InStream#(numeric type k, type tok_t, type record_t);
// call this method to check the no. credit tokens available for each queue
method Vector#(k,tok_t) getTokInfo();
// call this method to reserve 'amnt' credit tokens for queue (stream) 'idx'
// notes: 1) amnt must be less than tokens implies by getTokInfo
// 2) caller must guarantee they put amnt records into the sort tree in the future
method Action putDeqTok(Bit#(TLog#(k)) idx, tok_t amnt);
// call this method to put the data record into the sort tree
method Action putRecord(Bit#(TLog#(k)) idx, record_t record);
endinterface
interface OutStream#(numeric type k, type tok_t, type record_t);
// call this method to tell its user no. credit tokens available
method Action putTokInfo (Vector#(k,tok_t) tokInfo);
// call this method to see how many credit tokens and which queue the user want to reserve
// notes: 1) amnt must be less than tokens implies by getTokInfo
// 2) caller must guarantee they put amnt records into the sort tree in the future
method Tuple2#(Bit#(TLog#(k)),tok_t) getDeqTok();
// call this method to see whether user has record coming out
method Tuple2#(Bit#(TLog#(k)),record_t) getRecord();
endinterface
// define the interface for a k-merge sort (i.e. merge
// k sorted streams into 1 sorted stream)
interface SortTree#(numeric type k, type tok_t, type record_t);
// the input stream
interface InStream#(k, tok_t, record_t) inStream;
// the output merged data
method ActionValue#(record_t) getRecord();
endinterface
// interface for intermediate levels of the tree
interface SortLevel#(numeric type k, numeric type k_next,
type tok_t, type next_tok_t,
type record_t);
// the input stream
interface InStream#(k, tok_t, record_t) inStream;
// the output stream
interface OutStream#(k_next, next_tok_t, record_t) outStream;
endinterface
// the scheduler interface, the scheduler try to collect credit tokens information
// from the next level and the current level of the sort and then decide which
// stream to process next
interface Scheduler#(numeric type k, type tok_t, type next_tok_t);
// give the scheduler usage information so that it can pick the next to process
(* always_ready *) method Action putInfo(Vector#(k,next_tok_t) nextTok,
Vector#(k,tok_t) tok0,
Vector#(k,tok_t) tok1);
// return the next stream to be processed, if return tagged Invalid = do nothing
(* always_ready *) method Maybe#(Bit#(TLog#(k))) getNext();
endinterface
//////////////////////////////////////////////////////////////////////////
// auxiliary functions
function Bool notValid(Maybe#(a) i);
return !isValid(i);
endfunction
function Bool largerThan(Bit#(sz) a, Bit#(sz) val);
return val > a;
endfunction
function Bool and3(Bool a, Bool b, Bool c);
return a && b && c;
endfunction
function Tuple2#(Bool,a) chooseFirstIfPossible(Tuple2#(Bool,a) fst,
Tuple2#(Bool,a) snd);
return tpl_1(fst) ? fst : snd;
endfunction
function Bool isSmaller(d_t a, d_t b)
provisos (Bits#(d_t,d_sz),
Mul#(8,q_sz,d_sz),
Add#(1,xxA,d_sz));
Vector#(8,Bit#(q_sz)) aVec = reverse(unpack(pack(a)));
Vector#(8,Bit#(q_sz)) bVec = reverse(unpack(pack(b)));
function Tuple2#(Bool,Bool) getLargerAndEqual(Tuple2#(Bool,Bool) aTup, Tuple2#(Bool,Bool) bTup);
return tuple2((tpl_1(aTup) || (tpl_2(aTup) && tpl_1(bTup))),
(tpl_2(aTup) && tpl_2(bTup)));
endfunction
let res = tpl_1(fold(getLargerAndEqual,
zip(zipWith(\< ,aVec,bVec),
zipWith(\== ,aVec,bVec))));
return res;
endfunction
//////////////////////////////////////////////////////////////////////////
// Module definitions
//instance Connectable
instance Connectable#(OutStream#(k,tok_t,record_t), InStream#(k,tok_t,record_t));
module mkConnection#(OutStream#(k,tok_t,record_t) out,
InStream#(k,tok_t,record_t) in) (Empty);
rule connectTokInfo(True);
out.putTokInfo(in.getTokInfo());
endrule
rule connectDeqTok(True);
match {.idx, .amnt} = out.getDeqTok();
in.putDeqTok(idx,amnt);
endrule
rule connectRecord(True);
let tup = out.getRecord();
in.putRecord(tpl_1(tup),tpl_2(tup));
endrule
endmodule
endinstance
// a scheduler which the scheduling decision is return in the same cycle
module mkZeroCycleScheduler (Scheduler#(k_next,Bit#(sz),Bit#(sz_next)))
provisos (Add#(1,xxA,k_next));
Reg#(Maybe#(Bit#(TLog#(k_next)))) last <- mkReg(tagged Invalid);
Wire#(Maybe#(Bit#(TLog#(k_next)))) getNextW <- mkDWire(tagged Invalid);
method Action putInfo(Vector#(k_next,Bit#(sz_next)) nextTok,
Vector#(k_next,Bit#(sz)) tok0,
Vector#(k_next,Bit#(sz)) tok1);
let idx = fromMaybe(?,last);
let okNext = map(largerThan(0),nextTok);
let ok0 = map(largerThan(0),tok0);
ok0[idx] = isValid(last) ? False : ok0[idx];
let ok1 = map(largerThan(0),tok1);
let okVec0 = zipWith3(and3,okNext,ok0,ok1);
Vector#(k_next,Integer) intVec = genVector();
let vec0 = zip(okVec0,intVec);
let res0 = fold(chooseFirstIfPossible,vec0);
let dec = tpl_1(res0) ? tagged Valid fromInteger(tpl_2(res0)) :
tagged Invalid;
last <= dec;
getNextW <= dec;
if(`SortDebug0) $display("%m scheduler choose ok %d idx %d",isValid(dec),fromMaybe(?,dec));
endmethod
method Maybe#(Bit#(TLog#(k_next))) getNext();
return getNextW;
endmethod
endmodule
// a scheduler which the scheduling decision is returned one cycle later
module mkOneCycleScheduler (Scheduler#(k_next,Bit#(sz),Bit#(sz_next)))
provisos (Add#(1,xxA,k_next));
Reg#(Maybe#(Bit#(TLog#(k_next)))) last <- mkReg(tagged Invalid);
Reg#(Maybe#(Bit#(TLog#(k_next)))) sndLast <- mkReg(tagged Invalid);
Reg#(Maybe#(Bit#(TLog#(k_next)))) sRes0 <- mkReg(tagged Invalid);
Reg#(Maybe#(Bit#(TLog#(k_next)))) sRes1 <- mkReg(tagged Invalid);
Wire#(Maybe#(Bit#(TLog#(k_next)))) getNextW <- mkDWire(tagged Invalid);
rule choose(True);
let chk1 = (sRes1 != last) && (sRes1 != sndLast);
let next = chk1 ? sRes1 : sRes0;
sndLast <= last;
last <= next;
getNextW <= next;
if(`SortDebug0) $display("%m scheduler choose ok %d idx %d",isValid(next),fromMaybe(?,next));
endrule
method Action putInfo(Vector#(k_next,Bit#(sz_next)) nextTok,
Vector#(k_next,Bit#(sz)) tok0,
Vector#(k_next,Bit#(sz)) tok1);
let okNext = map(largerThan(2),nextTok);
let ok0 = map(largerThan(2),tok0);
let ok1 = map(largerThan(2),tok1);
let okVec0 = zipWith3(and3,okNext,ok0,ok1);
Vector#(k_next,Integer) intVec = genVector();
let vec0 = zip(okVec0,intVec);
let res0 = fold(chooseFirstIfPossible,vec0);
let dec0 = tpl_1(res0) ? tagged Valid fromInteger(tpl_2(res0)) :
tagged Invalid;
let okNext1 = map(largerThan(0),nextTok);
let ok2 = map(largerThan(0),tok0);
let ok3 = map(largerThan(0),tok1);
let okVec1 = zipWith3(and3,okNext1,ok2,ok3);
let vec1 = zip(okVec1,intVec);
let res1 = fold(chooseFirstIfPossible,vec1);
let dec1 = tpl_1(res1) ? tagged Valid fromInteger(tpl_2(res1)) :
tagged Invalid;
sRes0 <= dec0;
sRes1 <= dec1;
endmethod
method Maybe#(Bit#(TLog#(k_next))) getNext();
return getNextW;
endmethod
endmodule
// a scheduler which the scheduling decision is returned one cycle later
module mkOneCycleScheduler2 (Scheduler#(k_next,Bit#(sz),Bit#(sz_next)))
provisos (Add#(1,xxA,k_half),
Div#(k_next,2,k_half),
Add#(k_half,k_half,k_next));
Reg#(Maybe#(Bit#(TLog#(k_next)))) last <- mkReg(tagged Invalid);
Reg#(Maybe#(Bit#(TLog#(k_next)))) sndLast <- mkReg(tagged Invalid);
Reg#(Maybe#(Bit#(TLog#(k_next)))) sRes0 <- mkReg(tagged Invalid);
Reg#(Maybe#(Bit#(TLog#(k_next)))) sRes1 <- mkReg(tagged Invalid);
Reg#(Maybe#(Bit#(TLog#(k_next)))) sRes2 <- mkReg(tagged Invalid);
Reg#(Maybe#(Bit#(TLog#(k_next)))) sRes3 <- mkReg(tagged Invalid);
Reg#(Bool) round <- mkReg(False);
Wire#(Maybe#(Bit#(TLog#(k_next)))) getNextW <- mkDWire(tagged Invalid);
rule choose(True);
// let chk2 = (sRes2 != last) && (sRes2 != sndLast);
// let chk3 = (sRes3 != last) && (sRes3 != sndLast);
// let next0 = chk2 ? sRes2 : sRes0;
// let next1 = chk3 ? sRes3 : sRes1;
// let next3 = isValid(next0) ? next0 : next1;
// let next4 = isValid(next1) ? next1 : next0;
// let next = round ? next3 : next4;
let chk2 = (sRes2 != last) && (sRes2 != sndLast);
let chk3 = (sRes3 != last) && (sRes3 != sndLast);
let next0 = chk2 ? sRes2 : sRes0;
let next1 = chk3 ? sRes3 : sRes1;
let next = round ? next0 : next1;
sndLast <= last;
last <= next;
getNextW <= next;
round <= !round;
if(`SortDebug0) $display("%m scheduler choose ok %d idx %d",isValid(next),fromMaybe(?,next));
endrule
method Action putInfo(Vector#(k_next,Bit#(sz_next)) nextTok,
Vector#(k_next,Bit#(sz)) tok0,
Vector#(k_next,Bit#(sz)) tok1);
// let okNext = map(largerThan(2),nextTok);
// let ok0 = map(largerThan(2),tok0);
// let ok1 = map(largerThan(2),tok1);
// let okVec = zipWith3(and3,okNext,ok0,ok1);
Vector#(k_next,Integer) intVec = genVector();
// let vec = zip(okVec,intVec);
// Vector#(k_half,Tuple2#(Bool,Integer)) vec0 = take(vec);
// Vector#(k_half,Tuple2#(Bool,Integer)) vec1 = takeTail(vec);
// let res0 = fold(chooseFirstIfPossible,vec0);
// let res1 = fold(chooseFirstIfPossible,vec1);
// let dec0 = tpl_1(res0) ? tagged Valid fromInteger(tpl_2(res0)) :
// tagged Invalid;
// let dec1 = tpl_1(res1) ? tagged Valid fromInteger(tpl_2(res1)) :
// tagged Invalid;
let okNext1 = map(largerThan(0),nextTok);
let ok2 = map(largerThan(0),tok0);
let ok3 = map(largerThan(0),tok1);
let okVec1 = zipWith3(and3,okNext1,ok2,ok3);
let vecc = zip(okVec1,intVec);
Vector#(k_half,Tuple2#(Bool,Integer)) vec2 = take(vecc);
Vector#(k_half,Tuple2#(Bool,Integer)) vec3 = takeTail(vecc);
let res2 = fold(chooseFirstIfPossible,vec2);
let res3 = fold(chooseFirstIfPossible,vec3);
let dec2 = tpl_1(res2) ? tagged Valid fromInteger(tpl_2(res2)) :
tagged Invalid;
let dec3 = tpl_1(res3) ? tagged Valid fromInteger(tpl_2(res3)) :
tagged Invalid;
// sRes0 <= dec0;
// sRes1 <= dec1;
sRes2 <= dec2;
sRes3 <= dec3;
endmethod
method Maybe#(Bit#(TLog#(k_next))) getNext();
return getNextW;
endmethod
endmodule
// bram time multiplex merger
module [Module] mkBRAMOneLevelMerger#(Bit#(fifo_sz) dntcare,
function Bool isEOS(record_t rec), // is end of stream token?
function val_t extractVal(record_t rec), // extract value from record
function Module#(Scheduler#(k_next,Bit#(TLog#(TAdd#(fifo_sz,1))),next_tok_t))
mkScheduler,
function Module#(VLevelFIFO#(k_next,fifo_sz,record_t))
mkBRAMVLevelFIFO)
(SortLevel#(k, k_next, Bit#(TLog#(TAdd#(fifo_sz,1))), next_tok_t, record_t))
provisos (Bits#(record_t,r_sz),
Ord#(val_t),
Bits#(val_t,val_sz),
Div#(val_sz,2,h_val_sz),
Mul#(8,q_val_sz,val_sz),
Add#(h_val_sz,h_val_sz,val_sz),
Add#(1,xxB,val_sz),
Add#(k_next,k_next,k), // k = 2 x k_next
Add#(xxA,TLog#(k_next),TLog#(k)),
Bits#(next_tok_t,next_tok_sz),
Literal#(next_tok_t));
// input queues
VLevelFIFO#(k_next,fifo_sz,record_t) inFstHalf <- mkBRAMVLevelFIFO();
VLevelFIFO#(k_next,fifo_sz,record_t) inSndHalf <- mkBRAMVLevelFIFO();
// wire storing the output value
Wire#(Maybe#(Tuple2#(Bit#(TLog#(k_next)),record_t))) outW <- mkDWire(tagged Invalid);
// wire storing whether the output has been read
Wire#(Bool) willDeqW <- mkDWire(False);
Wire#(Vector#(k_next,next_tok_t)) nextTokW <- mkDWire(?);
Wire#(Maybe#(Bit#(TLog#(k_next)))) getDeqTokW <- mkDWire(tagged Invalid);
FIFO#(Bit#(TLog#(k_next))) reqQ <- mkFIFO();
Scheduler#(k_next,Bit#(TLog#(TAdd#(fifo_sz,1))),next_tok_t) scheduler <- mkScheduler();
rule feedScheduler(True);
scheduler.putInfo(nextTokW,inFstHalf.used(),inSndHalf.used());
endrule
rule nextToProcess(True);
let res = scheduler.getNext();
let idx = fromMaybe(?,res);
getDeqTokW <= res;
// do the following read anyway...just don't get answer if the chk fail (cut critical path)
inFstHalf.firstReq(idx);
inSndHalf.firstReq(idx);
if (isValid(res)) // scheduler said we should do the next thing
begin
reqQ.enq(idx);
end
endrule
rule compares(True);
let in0 = inFstHalf.firstResp();
let in1 = inSndHalf.firstResp();
let eos0 = isEOS(in0);
let eos1 = isEOS(in1);
let v0 = extractVal(in0);
let v1 = extractVal(in1);
let cmp = isSmaller(v0,v1);
let idx = reqQ.first();
reqQ.deq();
if (eos0)
begin
outW <= tagged Valid tuple2(idx,in1); // always pass in1 data
if (eos1)
begin
inFstHalf.deq(idx);
inSndHalf.deq(idx);
end
else
begin
inSndHalf.deq(idx);
end
end
else
begin
if (eos1 || cmp)
begin
outW <= tagged Valid tuple2(idx,in0);
inFstHalf.deq(idx);
end
else
begin
outW <= tagged Valid tuple2(idx,in1);
inSndHalf.deq(idx);
end
end
if(`SortDebug0) $display("%m EOS0 %d",eos0);
if(`SortDebug0) $display("%m EOS1 %d",eos1);
if(`SortDebug0) $display("%m v0 %d",v0);
if(`SortDebug0) $display("%m v1 %d",v1);
endrule
// interface methods
interface InStream inStream;
method Vector#(k,Bit#(TLog#(TAdd#(fifo_sz,1)))) getTokInfo();
return append(inFstHalf.free(),inSndHalf.free());
endmethod
// this method is unguarded, so need to check getTokInfo before calling this
method Action putDeqTok(Bit#(TLog#(k)) idx, Bit#(TLog#(TAdd#(fifo_sz,1))) amnt);
let m = fromInteger(valueOf(TLog#(k))-1);
let tidx = truncate(idx);
if (idx[m:m] == 0)
inFstHalf.decrFree(tidx,amnt);
else
inSndHalf.decrFree(tidx,amnt);
endmethod
method Action putRecord(Bit#(TLog#(k)) idx, record_t record);
let m = fromInteger(valueOf(TLog#(k))-1);
let tidx = truncate(idx);
if (idx[m:m] == 0)
inFstHalf.enq(tidx,record);
else
inSndHalf.enq(tidx,record);
endmethod
endinterface
interface OutStream outStream;
method Action putTokInfo (Vector#(k_next,next_tok_t) nextTok);
nextTokW <= nextTok;
endmethod
method Tuple2#(Bit#(TLog#(k_next)),next_tok_t) getDeqTok() if (isValid(getDeqTokW));
return tuple2(fromMaybe(?,getDeqTokW),1);
endmethod
method Tuple2#(Bit#(TLog#(k_next)),record_t) getRecord() if (isValid(outW));
return fromMaybe(?,outW);
endmethod
endinterface
endmodule
// a non-bram version of a 2-to-1 merger. this one spend zero time in scheduling
module mkTwoToOneMerger#(function Bool isEOS(record_t rec), // is end of stream token?
function val_t extractVal(record_t rec)) // extract value from record
(SortTree#(2,Bit#(2), record_t))
provisos (Bits#(record_t,r_sz),
Ord#(val_t),
Bits#(val_t,val_sz),
Add#(1,xxA,val_sz),
Mul#(8,q_val_sz,val_sz),
Div#(val_sz,2,h_val_sz),
Add#(h_val_sz,h_val_sz,val_sz));
// input queues
Vector#(2,FIFOF#(record_t)) inQ <- replicateM(mkSizedFIFOF(2));
FIFO#(record_t) outQ <- mkSizedFIFO(2);
EHRReg#(2,Vector#(2,Bit#(2))) freeReg <- mkEHRReg(replicate(2));
// wire storing the output value
Wire#(Maybe#(Tuple2#(Bit#(0),record_t))) outW <- mkDWire(tagged Invalid);
Wire#(Maybe#(Bit#(1))) enqIdx <- mkDWire(tagged Invalid);
Wire#(record_t) enqVal <- mkDWire(?);
rule compares(True);
let in0 = inQ[0].first();
let in1 = inQ[1].first();
let eos0 = isEOS(in0);
let eos1 = isEOS(in1);
let v0 = extractVal(in0);
let v1 = extractVal(in1);
let cmp = isSmaller(v0, v1);
Vector#(2,Bit#(2)) newFreeReg = newVector();
newFreeReg = freeReg[1];
if (eos0)
begin
outQ.enq(in1); // always pass in1 data
if (eos1)
begin
inQ[0].deq();
newFreeReg[0] = newFreeReg[0] + 1;
inQ[1].deq();
newFreeReg[1] = newFreeReg[1] + 1;
end
else
begin
inQ[1].deq();
newFreeReg[1] = newFreeReg[1] + 1;
end
end
else
begin
if (eos1 || cmp)
begin
outQ.enq(in0);
inQ[0].deq();
newFreeReg[0] = newFreeReg[0] + 1;
end
else
begin
outQ.enq(in1);
inQ[1].deq();
newFreeReg[1] = newFreeReg[1] + 1;
end
end
freeReg[1] <= newFreeReg;
if(`SortDebug1) $display("%m EOS0 %d",eos0);
if(`SortDebug1) $display("%m EOS1 %d",eos1);
if(`SortDebug1) $display("%m v0 %d",v0);
if(`SortDebug1) $display("%m v1 %d",v1);
if(`SortDebug1) $display("%m compare newFreeReg0 %x, newFreeReg1 %x",newFreeReg[0],newFreeReg[1]);
endrule
rule printState (True);
if(`SortDebug1) $display("%m freeReg0 %d",freeReg[0][0]);
if(`SortDebug1) $display("%m freeReg1 %d",freeReg[0][1]);
if(`SortDebug1) $display("%m inQ0 first %d",inQ[0].first());
if(`SortDebug1) $display("%m inQ1 first %d",inQ[1].first());
if(`SortDebug1) $display("%m outQ first %d",outQ.first());
endrule
rule processPutRecord(isValid(enqIdx));
let idx = fromMaybe(?,enqIdx);
inQ[idx].enq(enqVal);
if(`SortDebug1) $display("%m processPutRecord to fifo %d, record %x",idx,enqVal);
endrule
// interface methods
interface InStream inStream;
method Vector#(2,Bit#(2)) getTokInfo();
return freeReg[0];
endmethod
// this method is unguarded, so need to check getTokInfo before calling this
method Action putDeqTok(Bit#(1) idx, Bit#(2) amnt);
Vector#(2,Bit#(2)) newFreeReg = newVector();
newFreeReg = freeReg[0];
newFreeReg[idx] = newFreeReg[idx] - amnt;
freeReg[0] <= newFreeReg;
if(`SortDebug1) $display("%m putDeqTok newFreeReg0 %x, newFreeReg1 %x",newFreeReg[0],newFreeReg[1]);
endmethod
method Action putRecord(Bit#(1) idx, record_t record);
enqIdx <= tagged Valid idx;
enqVal <= record;
if(`SortDebug1) $display("%m putRecord to fifo %d, record %x",idx,record);
endmethod
endinterface
method ActionValue#(record_t) getRecord();
outQ.deq();
if(`SortDebug1) $display("%m getRecord record %x",outQ.first());
return outQ.first();
endmethod
endmodule
1.1 cryptosorter/memocodeDesignContest2008/sort/SortTree128.bsv
http://www.opencores.org/cvsweb.shtml/cryptosorter/memocodeDesignContest2008/sort/SortTree128.bsv?rev=1.1&content-type=text/x-cvsweb-markup
Index: SortTree128.bsv
===================================================================
//----------------------------------------------------------------------//
// The MIT License
//
// Copyright (c) 2008 Alfred Man Cheuk Ng, mcn02@m...
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
//----------------------------------------------------------------------//
// import standard librarys
import Connectable::*;
import GetPut::*;
import FIFO::*;
import StmtFSM::*;
import Vector::*;
// import self-made library
import BRAMVLevelFIFO::*;
import EHRReg::*;
import VLevelFIFO::*;
import Sort::*;
import BRAMLevel7Merger::*;
import BRAMLevel6Merger::*;
import BRAMLevel5Merger::*;
import BRAMLevel4Merger::*;
import BRAMLevel3Merger::*;
import BRAMLevel2Merger::*;
import Level1Merger::*;
typedef 5 TOK_SZ;
(* synthesize *)
module mkSortTree128 (SortTree#(128,Bit#(TOK_SZ),Maybe#(Bit#(128))));
let level7Merger <- mkBRAMLevel7MergerInstance();
let level6Merger <- mkBRAMLevel6MergerInstance();
let level5Merger <- mkBRAMLevel5MergerInstance();
let level4Merger <- mkBRAMLevel4MergerInstance();
let level3Merger <- mkBRAMLevel3MergerInstance();
let level2Merger <- mkBRAMLevel2MergerInstance();
let level1Merger <- mkLevel1MergerInstance();
mkConnection(level7Merger.outStream,level6Merger.inStream);
mkConnection(level6Merger.outStream,level5Merger.inStream);
mkConnection(level5Merger.outStream,level4Merger.inStream);
mkConnection(level4Merger.outStream,level3Merger.inStream);
mkConnection(level3Merger.outStream,level2Merger.inStream);
mkConnection(level2Merger.outStream,level1Merger.inStream);
interface inStream = level7Merger.inStream;
method getRecord = level1Merger.getRecord;
endmodule
1.1 cryptosorter/memocodeDesignContest2008/sort/SortTree16.bsv
http://www.opencores.org/cvsweb.shtml/cryptosorter/memocodeDesignContest2008/sort/SortTree16.bsv?rev=1.1&content-type=text/x-cvsweb-markup
Index: SortTree16.bsv
===================================================================
//----------------------------------------------------------------------//
// The MIT License
//
// Copyright (c) 2008 Alfred Man Cheuk Ng, mcn02@m...
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
//----------------------------------------------------------------------//
// import standard librarys
import Connectable::*;
import GetPut::*;
import FIFO::*;
import StmtFSM::*;
import Vector::*;
// import self-made library
import BRAMVLevelFIFO::*;
import EHRReg::*;
import VLevelFIFO::*;
import Sort::*;
import BRAMLevel4Merger::*;
import BRAMLevel3Merger::*;
import BRAMLevel2Merger::*;
import Level1Merger::*;
typedef 4 FIFO_SZ;
typedef 3 TOK_SZ;
(* synthesize *)
module mkSortTree16 (SortTree#(16,Bit#(TOK_SZ),Maybe#(Bit#(128))));
let level4Merger <- mkBRAMLevel4MergerInstance();
let level3Merger <- mkBRAMLevel3MergerInstance();
let level2Merger <- mkBRAMLevel2MergerInstance();
let level1Merger <- mkLevel1MergerInstance();
mkConnection(level4Merger.outStream,level3Merger.inStream);
mkConnection(level3Merger.outStream,level2Merger.inStream);
mkConnection(level2Merger.outStream,level1Merger.inStream);
interface inStream = level4Merger.inStream;
method getRecord = level1Merger.getRecord;
endmodule
1.1 cryptosorter/memocodeDesignContest2008/sort/SortTree256.bsv
http://www.opencores.org/cvsweb.shtml/cryptosorter/memocodeDesignContest2008/sort/SortTree256.bsv?rev=1.1&content-type=text/x-cvsweb-markup
Index: SortTree256.bsv
===================================================================
//----------------------------------------------------------------------//
// The MIT License
//
// Copyright (c) 2008 Alfred Man Cheuk Ng, mcn02@m...
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
//----------------------------------------------------------------------//
// import standard librarys
import Connectable::*;
import GetPut::*;
import FIFO::*;
import StmtFSM::*;
import Vector::*;
// import self-made library
import BRAMVLevelFIFO::*;
import EHRReg::*;
import VLevelFIFO::*;
import Sort::*;
import BRAMLevel8Merger::*;
import BRAMLevel7Merger::*;
import BRAMLevel6Merger::*;
import BRAMLevel5Merger::*;
import BRAMLevel4Merger::*;
import BRAMLevel3Merger::*;
import BRAMLevel2Merger::*;
import Level1Merger::*;
(* synthesize *)
module mkSortTree256 (SortTree#(256,Bit#(5),Maybe#(Bit#(128))));
let level8Merger <- mkBRAMLevel8MergerInstance();
let level7Merger <- mkBRAMLevel7MergerInstance();
let level6Merger <- mkBRAMLevel6MergerInstance();
let level5Merger <- mkBRAMLevel5MergerInstance();
let level4Merger <- mkBRAMLevel4MergerInstance();
let level3Merger <- mkBRAMLevel3MergerInstance();
let level2Merger <- mkBRAMLevel2MergerInstance();
let level1Merger <- mkLevel1MergerInstance();
mkConnection(level8Merger.outStream,level7Merger.inStream);
mkConnection(level7Merger.outStream,level6Merger.inStream);
mkConnection(level6Merger.outStream,level5Merger.inStream);
mkConnection(level5Merger.outStream,level4Merger.inStream);
mkConnection(level4Merger.outStream,level3Merger.inStream);
mkConnection(level3Merger.outStream,level2Merger.inStream);
mkConnection(level2Merger.outStream,level1Merger.inStream);
interface inStream = level8Merger.inStream;
method getRecord = level1Merger.getRecord;
endmodule
1.1 cryptosorter/memocodeDesignContest2008/sort/SortTree64.bsv
http://www.opencores.org/cvsweb.shtml/cryptosorter/memocodeDesignContest2008/sort/SortTree64.bsv?rev=1.1&content-type=text/x-cvsweb-markup
Index: SortTree64.bsv
===================================================================
//----------------------------------------------------------------------//
// The MIT License
//
// Copyright (c) 2008 Alfred Man Cheuk Ng, mcn02@m...
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
//----------------------------------------------------------------------//
// import standard librarys
import Connectable::*;
import GetPut::*;
import FIFO::*;
import StmtFSM::*;
import Vector::*;
// import self-made library
import BRAMVLevelFIFO::*;
import EHRReg::*;
import VLevelFIFO::*;
import Sort::*;
import BRAMLevel6Merger::*;
import BRAMLevel5Merger::*;
import BRAMLevel4Merger::*;
import BRAMLevel3Merger::*;
import BRAMLevel2Merger::*;
import Level1Merger::*;
typedef 5 TOK_SZ;
(* synthesize *)
module mkSortTree64 (SortTree#(64,Bit#(TOK_SZ),Maybe#(Bit#(128))));
let level6Merger <- mkBRAMLevel6MergerInstance();
let level5Merger <- mkBRAMLevel5MergerInstance();
let level4Merger <- mkBRAMLevel4MergerInstance();
let level3Merger <- mkBRAMLevel3MergerInstance();
let level2Merger <- mkBRAMLevel2MergerInstance();
let level1Merger <- mkLevel1MergerInstance();
mkConnection(level6Merger.outStream,level5Merger.inStream);
mkConnection(level5Merger.outStream,level4Merger.inStream);
mkConnection(level4Merger.outStream,level3Merger.inStream);
mkConnection(level3Merger.outStream,level2Merger.inStream);
mkConnection(level2Merger.outStream,level1Merger.inStream);
interface inStream = level6Merger.inStream;
method getRecord = level1Merger.getRecord;
endmodule
1.1 cryptosorter/memocodeDesignContest2008/sort/SortTreeTestbench.bsv
http://www.opencores.org/cvsweb.shtml/cryptosorter/memocodeDesignContest2008/sort/SortTreeTestbench.bsv?rev=1.1&content-type=text/x-cvsweb-markup
Index: SortTreeTestbench.bsv
===================================================================
// import standard librarys
import Connectable::*;
import GetPut::*;
import FIFO::*;
import StmtFSM::*;
import Vector::*;
// import self-made library
import BRAMVLevelFIFO::*;
import VLevelFIFO::*;
import Sort::*;
import LFSR::*;
import Memocode08Types::*;
import SortTree16::*;
import SortTree64::*;
typedef 16 KMerges;
typedef enum{
Uninitialized,
Burst,
Idle,
FIFOStage,
FIFOIdle,
Done
} State deriving (Bits,Eq);
module mkSortTreeTestbench(Empty);
Vector#(KMerges,FIFO#(Record)) resultFIFOs <- replicateM(mkSizedFIFO(valueof(KMerges)+1));
// SortTree#(KMerges,1,Bit#(7),Bit#(1),Maybe#(Bit#(128))) sortTree <- mkBRAMSort16;
let sortTree <- mkSortTree16;
Reg#(Bit#(TLog#(KMerges))) slabCount <- mkReg(0);
Reg#(Bit#(TMul#(2,TLog#(KMerges)))) finalCount <- mkReg(0);
Reg#(State) stateMeta <- mkReg(Burst);
Reg#(Bit#(128)) lastValue <- mkReg(0);
Reg#(Bit#(64)) cycleCnt <- mkReg(0);
Reg#(Bit#(TLog#(TAdd#(KMerges,1)))) recvCount <- mkReg(0);
Reg#(Bit#(TLog#(TAdd#(KMerges,1)))) sendCount <- mkReg(0);
Reg#(Bit#(8)) nextValue <- mkReg(0);
rule incrCycle (True);
cycleCnt <= cycleCnt + 1;
$display("cycle %d",cycleCnt);
endrule
rule getTokInfo (True);
let tokInfo = sortTree.inStream.getTokInfo();
for (Integer i = 0; i < valueOf(KMerges); i = i + 1)
$display("Instream Tok Info idx %d tok %d",i,tokInfo[i]);
endrule
for(Integer i = 0; i < valueof(KMerges); i = i + 1)
begin
Reg#(Bool) initialized <- mkReg(False);
Reg#(Bit#(TLog#(KMerges))) count <- mkReg(0);
Reg#(State) state <- mkReg(Burst);
rule push ((state == Burst) && ((sortTree.inStream.getTokInfo())[i] > 1));
$display("Sender %d is Bursting", i);
sortTree.inStream.putDeqTok(fromInteger(i),2);
sortTree.inStream.putRecord(fromInteger(i),
tagged Valid (zeroExtend(nextValue)));
nextValue <= nextValue + 101; // 101 is rel. prime to 256, and so will generate the U256 group
state <= Idle;
endrule
// rule endpush ((state == Idle) && ((sortTree.inStream.getTokInfo())[i] > 0));
rule endpush (state == Idle);
$display("Sender %d is Idling", i);
sortTree.inStream.putRecord(fromInteger(i), tagged Invalid);
count <= count + 1;
if(count + 1 == 0)
begin
state <= FIFOStage;
sendCount <= sendCount + 1;
end
else
begin
state <= Burst;
end
endrule
rule fifopush ((sendCount == 16) && (state == FIFOStage) && ((sortTree.inStream.getTokInfo())[i] > 0));
$display("Sender %d is FIFOStage",i);
sortTree.inStream.putDeqTok(fromInteger(i),1);
resultFIFOs[i].deq;
sortTree.inStream.putRecord(fromInteger(i), tagged Valid resultFIFOs[i].first);
count <= count + 1;
if(count + 1 == 0)
begin
state <= FIFOIdle;
end
else
begin
state <= FIFOStage;
end
endrule
rule endfifo ((state == FIFOIdle)&& ((sortTree.inStream.getTokInfo())[i] > 0));
$display("Sender %d is FIFOIdle",i);
sortTree.inStream.putDeqTok(fromInteger(i),1);
sortTree.inStream.putRecord(fromInteger(i), tagged Invalid);
state <= Done;
endrule
end
rule readOutResults(stateMeta == Burst);
let outdata <- sortTree.getRecord();
if(outdata matches tagged Valid .data)
begin
$display("Getting a slab result %d, recv count %d",data,recvCount);
resultFIFOs[slabCount].enq(data);
recvCount <= recvCount + 1;
if(lastValue > data)
begin
$display("%m Error: %d > %d at %d", lastValue, data, finalCount);
$finish();
end
lastValue <= data;
end
else
begin
$display("Getting a end of stream token %d",recvCount);
slabCount <= slabCount + 1;
lastValue <= 0;
recvCount <= 0;
if (recvCount != fromInteger(valueOf(KMerges)))
begin
$display("error merge recv token too early %d", recvCount);
$finish();
end
if(slabCount + 1 == 0)
begin
stateMeta <= FIFOStage;
end
end
endrule
rule readOutResultsFinal(stateMeta == FIFOStage);
$display("%m Getting a result");
let outdata <- sortTree.getRecord();
if(outdata matches tagged Valid .data)
begin
finalCount <= finalCount + 1;
if(zeroExtend(finalCount) != data)
begin
$display("%m Error: %d != %d at %d", finalCount, data, finalCount);
$finish();
end
if(lastValue > data)
begin
$display("%m Error: %d > %d at %d", lastValue, data, finalCount);
$finish();
end
lastValue <= data;
end
else
begin
if(finalCount != 0)
begin
$display("%m Error: final Value: %d", finalCount);
$finish();
end
else
begin
let timeVal <- $time();
$display("%m PASSES at %d cycle %d", timeVal,cycleCnt);
$finish();
end
end
endrule
endmodule
1.1 cryptosorter/memocodeDesignContest2008/sort/SynthRegFiles.bsv
http://www.opencores.org/cvsweb.shtml/cryptosorter/memocodeDesignContest2008/sort/SynthRegFiles.bsv?rev=1.1&content-type=text/x-cvsweb-markup
Index: SynthRegFiles.bsv
===================================================================
import RegFile::*;
1.1 cryptosorter/memocodeDesignContest2008/sort/VLevelFIFO.bsv
http://www.opencores.org/cvsweb.shtml/cryptosorter/memocodeDesignContest2008/sort/VLevelFIFO.bsv?rev=1.1&content-type=text/x-cvsweb-markup
Index: VLevelFIFO.bsv
===================================================================
//----------------------------------------------------------------------//
// The MIT License
//
// Copyright (c) 2008 Alfred Man Cheuk Ng, mcn02@m...
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
//----------------------------------------------------------------------//
// import standard library
import DReg::*;
import FIFO::*;
import Vector::*;
// interface definition of a vector of logical fifos indexed by fifo_idx_t
// with data type data_t. Each fifos gives a usage report too
interface VLevelFIFO#(numeric type no_fifo,
numeric type fifo_sz,
type data_t);
// enq fifo idx
method Action enq(Bit#(TLog#(no_fifo)) idx, data_t data);
// deq fifo idx
method Action deq(Bit#(TLog#(no_fifo)) idx);
// read_req for first of fifo idx
method Action firstReq(Bit#(TLog#(no_fifo)) idx);
// first_resp
method data_t firstResp();
// clear all fifos
method Action clear();
// return no. elements in each fifo at the beginning of cycle
method Vector#(no_fifo,Bit#(TLog#(TAdd#(fifo_sz,1)))) used();
// return no. elements in each fifo at the end of cycle
// method Vector#(no_fifo,Bit#(TLog#(TAdd#(fifo_sz,1)))) used2();
// return no. enq credit tokens in each fifo
method Vector#(no_fifo,Bit#(TLog#(TAdd#(fifo_sz,1)))) free();
// decrement amnt of "enq credit tokens" of fifo idx
method Action decrFree(Bit#(TLog#(no_fifo)) idx, Bit#(TLog#(TAdd#(fifo_sz,1))) amnt);
endinterface
1.1 cryptosorter/memocodeDesignContest2008/sort/VLevelFIFOTester.bsv
http://www.opencores.org/cvsweb.shtml/cryptosorter/memocodeDesignContest2008/sort/VLevelFIFOTester.bsv?rev=1.1&content-type=text/x-cvsweb-markup
Index: VLevelFIFOTester.bsv
===================================================================
//----------------------------------------------------------------------//
// The MIT License
//
// Copyright (c) 2008 Alfred Man Cheuk Ng, mcn02@m...
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
//----------------------------------------------------------------------//
import DReg::*;
import FIFO::*;
import Vector::*;
import VLevelFIFO::*;
import BRAMVLevelFIFO::*;
import Memocode08Types::*;
import LFSR::*;
import FIFOF::*;
import FIFO::*;
import GetPut::*;
typedef 2 NumberFifos;
typedef 8 DepthFifos;
typedef enum {
Initialize,
Request,
Transmit
} TesterState deriving(Bits,Eq);
(* synthesize *)
module mkVLevelFIFOInstance(VLevelFIFO#(NumberFifos,DepthFifos,Record));
let mod <- mkBRAMVLevelFIFO();
return mod;
endmodule
module mkVLevelFIFOTester (Empty);
VLevelFIFO#(NumberFifos,DepthFifos,Record) fifo <- mkVLevelFIFOInstance;
Vector#(NumberFifos,FIFOF#(Record)) expectedVals <- replicateM(mkSizedFIFOF(valueof(DepthFifos)));
Reg#(Bit#(64)) reqsSent <- mkReg(0);
Reg#(Bit#(64)) reqsRxed <- mkReg(0);
rule haltAll;
Bit#(64) timeCount <- $time;
if(timeCount > 1010000)
begin
if(reqsSent == reqsRxed)
begin
$display("PASSED");
$finish;
end
else
begin
$display("Expected %d values, got %d", reqsSent, reqsRxed);
end
end
endrule
for(Integer i = 0; i < valueof(NumberFifos); i = i + 1)
begin
Reg#(TesterState) state <- mkReg(Initialize);
FIFO#(Bit#(0)) reqQ <- mkFIFO;
LFSR#(Bit#(16)) lfsr <- mkLFSR_16;
Reg#(Bit#(32)) counter <- mkReg(0);
Wire#(Bool) isDeqW <- mkDWire(False);
rule countUp;
counter <= counter + 1;
endrule
rule init(state == Initialize);
state <= Request;
lfsr.seed(fromInteger(i+1+valueof(NumberFifos)));
endrule
rule firstFifo((state == Request) && !isDeqW && (fifo.used[fromInteger(i)] > 0) && (counter % fromInteger(32*(i+1)) == 0));
$display("Calling first fifo %d", i);
fifo.firstReq(fromInteger(i));
reqQ.enq(?);
endrule
rule deqFifo(True);
isDeqW <= True;
reqQ.deq();
expectedVals[i].deq;
let deqData = fifo.firstResp();
fifo.deq(fromInteger(i));
if(deqData != zeroExtend(expectedVals[i].first))
begin
$display("Dequed: [%d] %h != %h", i, expectedVals[i].first, deqData);
$finish;
end
else
begin
reqsRxed <= reqsRxed + 1;
$display("Fifo %d had %d values", i, fifo.used[fromInteger(i)]);
end
endrule
end
// Send data out to the BRAM
for(Integer i = 0; i < valueof(NumberFifos); i = i + 1)
begin
LFSR#(Bit#(16)) lfsr <- mkLFSR_16;
Reg#(TesterState) state <- mkReg(Initialize);
Reg#(Bit#(32)) counter <- mkReg(0);
rule countUp;
counter <= counter + 1;
endrule
rule init(state == Initialize);
state <= Request;
lfsr.seed(fromInteger(i+1+valueof(ReadPortNum)));
endrule
rule sendRequest((state == Request) && (counter % fromInteger(32*(i+3)) == 0) && fifo.free[fromInteger(i)] > 0);
Bit#(64) timeCount <- $time;
if(timeCount < 1000000)
begin
if (fifo.free[fromInteger(i)] > 3)
begin
fifo.decrFree(fromInteger(i),4);
end
reqsSent <= reqsSent+1;
fifo.enq(fromInteger(i),zeroExtend(lfsr.value));
lfsr.next();
expectedVals[i].enq(zeroExtend(lfsr.value));
end
endrule
rule haltCheck (expectedVals[i].notEmpty);
Bit#(64) timeCount <- $time;
if(timeCount > 11000000)
begin
$display("Writer[%d] stalled out", i);
$finish;
end
endrule
end
endmodule
/****
****
****/
module mkVLevelFIFOTesterFull (Empty);
VLevelFIFO#(NumberFifos,DepthFifos,Record) fifo <- mkBRAMVLevelFIFO;
Vector#(NumberFifos,FIFOF#(Record)) expectedVals <- replicateM(mkSizedFIFOF(valueof(DepthFifos)));
Reg#(Bit#(64)) reqsSent <- mkReg(0);
Reg#(Bit#(64)) reqsRxed <- mkReg(0);
rule haltAll;
Bit#(64) timeCount <- $time;
if(timeCount > 1010000)
begin
if(reqsSent == reqsRxed)
begin
$display("PASSED");
$finish;
end
else
begin
$display("Expected %d values, got %d", reqsSent, reqsRxed);
end
end
endrule
for(Integer i = 0; i < valueof(NumberFifos); i = i + 1)
begin
Reg#(TesterState) state <- mkReg(Initialize);
FIFO#(Bit#(0)) reqQ <- mkFIFO;
LFSR#(Bit#(16)) lfsr <- mkLFSR_16;
Reg#(Bit#(32)) counter <- mkReg(0);
Reg#(Bool) okayToReq <- mkReg(True);
Wire#(Bool) isDeqW <- mkDWire(False);
rule countUp;
counter <= counter + 1;
endrule
rule init(state == Initialize);
state <= Request;
lfsr.seed(fromInteger(i+1+valueof(NumberFifos)));
endrule
rule firstFifo((state == Request) && !isDeqW && (fifo.used[fromInteger(i)] > 0) && (counter % fromInteger(32*(i+1)) == 0));
// rule firstFifo((state == Request) && okayToReq && (fifo.used[fromInteger(i)] > 0) && (counter % fromInteger(32*(i+1)) == 0));
fifo.firstReq(fromInteger(i));
// okayToReq <= False;
reqQ.enq(?);
endrule
rule deqFifo(True);
// rule deqFifo( !okayToReq && (fifo.used[fromInteger(i)] > 0));
isDeqW <= True;
reqQ.deq();
// okayToReq <= True;
expectedVals[i].deq;
let deqData = fifo.firstResp();
fifo.deq(fromInteger(i));
if(deqData != zeroExtend(expectedVals[i].first))
begin
$display("Dequed: [%d] %h != %h", i, expectedVals[i].first, deqData);
$finish;
end
else
begin
reqsRxed <= reqsRxed + 1;
$display("Fifo %d had %d values", i, fifo.used[fromInteger(i)]);
end
endrule
end
// Send data out to the BRAM
for(Integer i = 0; i < valueof(NumberFifos); i = i + 1)
begin
LFSR#(Bit#(16)) lfsr <- mkLFSR_16;
Reg#(TesterState) state <- mkReg(Initialize);
Reg#(Bit#(32)) counter <- mkReg(0);
Reg#(Bit#(TLog#(DepthFifos))) toSendCount <- mkReg(0);
rule countUp;
counter <= counter + 1;
endrule
rule init(state == Initialize);
state <= Request;
lfsr.seed(fromInteger(i+1+valueof(ReadPortNum)));
endrule
rule sendRequestStart((state == Request) && (toSendCount == 0) && (counter % fromInteger(32*(i+3)) == 0) && (fifo.free[fromInteger(i)] > 0));
Bit#(64) timeCount <- $time;
if(timeCount < 1000000)
begin
Bit#(TLog#(DepthFifos)) extras = truncate(fromInteger(i));
toSendCount <= truncate(fromInteger(i));
$display("Extra send rule: %d", extras);
fifo.enq(fromInteger(i),zeroExtend(lfsr.value));
fifo.decrFree(fromInteger(i),1);
reqsSent <= reqsSent + 1;
expectedVals[i].enq(zeroExtend(lfsr.value));
end
endrule
rule sendRequest(toSendCount > 0);
$display("Extra send rule");
toSendCount <= toSendCount - 1;
if(toSendCount - 1 == 0)
begin
lfsr.next();
end
reqsSent <= reqsSent + 1;
expectedVals[i].enq(zeroExtend(lfsr.value));
fifo.enq(fromInteger(i),zeroExtend(lfsr.value));
fifo.decrFree(fromInteger(i),1);
endrule
rule haltCheck (expectedVals[i].notEmpty);
Bit#(64) timeCount <- $time;
if(timeCount > 11000000)
begin
$display("Writer[%d] stalled out", i);
$finish;
end
endrule
end
endmodule
1.1 cryptosorter/memocodeDesignContest2008/sort/mkBRAMLevel2MergerInstance.sched
http://www.opencores.org/cvsweb.shtml/cryptosorter/memocodeDesignContest2008/sort/mkBRAMLevel2MergerInstance.sched?rev=1.1&content-type=text/x-cvsweb-markup
Index: mkBRAMLevel2MergerInstance.sched
===================================================================
=== Generated schedule for mkBRAMLevel2MergerInstance ===
Method schedule
---------------
Method: inStream_getTokInfo
Ready signal: res_inFstHalf_finishInit && res_inSndHalf_finishInit
Conflict-free: inStream_getTokInfo,
inStream_putDeqTok,
inStream_putRecord,
outStream_putTokInfo,
outStream_getDeqTok_fst,
outStream_getDeqTok_snd,
outStream_getRecord_fst,
outStream_getRecord_snd
Method: inStream_putDeqTok
Ready signal: res_inSndHalf_finishInit && res_inFstHalf_finishInit
Conflict-free: inStream_getTokInfo,
inStream_putRecord,
outStream_putTokInfo,
outStream_getDeqTok_fst,
outStream_getDeqTok_snd,
outStream_getRecord_fst,
outStream_getRecord_snd
Conflicts: inStream_putDeqTok
Method: inStream_putRecord
Ready signal: res_inSndHalf_finishInit && res_inFstHalf_finishInit
Conflict-free: inStream_getTokInfo,
inStream_putDeqTok,
outStream_putTokInfo,
outStream_getDeqTok_fst,
outStream_getDeqTok_snd,
outStream_getRecord_fst,
outStream_getRecord_snd
Conflicts: inStream_putRecord
Method: outStream_putTokInfo
Ready signal: True
Conflict-free: inStream_getTokInfo,
inStream_putDeqTok,
inStream_putRecord,
outStream_getRecord_fst,
outStream_getRecord_snd
Sequenced before (restricted): outStream_getDeqTok_fst,
outStream_getDeqTok_snd
Conflicts: outStream_putTokInfo
Method: outStream_getDeqTok_fst
Ready signal: res_getDeqTokW.whas && res_getDeqTokW.wget[1]
Conflict-free: inStream_getTokInfo,
inStream_putDeqTok,
inStream_putRecord,
outStream_getDeqTok_fst,
outStream_getDeqTok_snd,
outStream_getRecord_fst,
outStream_getRecord_snd
Sequenced after (restricted): outStream_putTokInfo
Method: outStream_getDeqTok_snd
Ready signal: res_getDeqTokW.whas && res_getDeqTokW.wget[1]
Conflict-free: inStream_getTokInfo,
inStream_putDeqTok,
inStream_putRecord,
outStream_getDeqTok_fst,
outStream_getDeqTok_snd,
outStream_getRecord_fst,
outStream_getRecord_snd
Sequenced after (restricted): outStream_putTokInfo
Method: outStream_getRecord_fst
Ready signal: res_outW.whas && res_outW.wget[130]
Conflict-free: inStream_getTokInfo,
inStream_putDeqTok,
inStream_putRecord,
outStream_putTokInfo,
outStream_getDeqTok_fst,
outStream_getDeqTok_snd,
outStream_getRecord_fst,
outStream_getRecord_snd
Method: outStream_getRecord_snd
Ready signal: res_outW.whas && res_outW.wget[130]
Conflict-free: inStream_getTokInfo,
inStream_putDeqTok,
inStream_putRecord,
outStream_putTokInfo,
outStream_getDeqTok_fst,
outStream_getDeqTok_snd,
outStream_getRecord_fst,
outStream_getRecord_snd
Rule schedule
-------------
Rule: res_compares
Predicate: res_inFstHalf_ugbram_bram.RDY_read_resp &&
res_inSndHalf_ugbram_bram.RDY_read_resp &&
res_inFstHalf_finishInit &&
res_inSndHalf_finishInit && res_reqQ.i_notEmpty
Blocking rules: (none)
Rule: res_nextToProcess
Predicate: res_inFstHalf_finishInit &&
res_inSndHalf_finishInit &&
((! res_scheduler_getNextW.whas) ||
(! res_scheduler_getNextW.wget[1]) ||
res_reqQ.i_notFull)
Blocking rules: (none)
Rule: res_feedScheduler
Predicate: (((res_nextTokW.whas
? res_nextTokW.wget[1:0]
: _) ==
2'd0) ||
res_inFstHalf_finishInit) &&
(((res_nextTokW.whas
? res_nextTokW.wget[1:0]
: _) ==
2'd0) ||
((res_scheduler_last[1]
? ! res_scheduler_last[0]
: _)
? res_scheduler_last[1] || (res_inFstHalf_usedReg[2:0] == 3'd0)
: (res_inFstHalf_usedReg[2:0] == 3'd0)) ||
res_inSndHalf_finishInit) &&
(((! ((res_nextTokW.whas
? res_nextTokW.wget[1:0]
: _) ==
2'd0)) &&
((res_scheduler_last[1]
? ! res_scheduler_last[0]
: _)
? (! res_scheduler_last[1]) &&
(! (res_inFstHalf_usedReg[2:0] == 3'd0))
: (! (res_inFstHalf_usedReg[2:0] == 3'd0))) &&
(! (res_inSndHalf_usedReg[2:0] == 3'd0)))
? res_inFstHalf_finishInit && res_inSndHalf_finishInit
: ((((res_nextTokW.whas
? res_nextTokW.wget[3:2]
: _) ==
2'd0) ||
res_inFstHalf_finishInit) &&
(((res_nextTokW.whas
? res_nextTokW.wget[3:2]
: _) ==
2'd0) ||
((res_scheduler_last[1]
? res_scheduler_last[0]
: _)
? res_scheduler_last[1] ||
((res_scheduler_last[1]
? ! res_scheduler_last[0]
: _)
? res_inFstHalf_usedReg[2:0] == 3'd0
: (res_inFstHalf_usedReg[5:3] == 3'd0))
: (res_inFstHalf_usedReg[5:3] == 3'd0)) ||
res_inSndHalf_finishInit)))
Blocking rules: (none)
Rule: res_inSndHalf_processDeq
Predicate: res_inSndHalf_finishInit &&
res_inSndHalf_deqIdx.whas && res_inSndHalf_deqIdx.wget[1]
Blocking rules: (none)
Rule: res_inSndHalf_processFirstReq
Predicate: res_inSndHalf_finishInit &&
res_inSndHalf_firstIdx.whas && res_inSndHalf_firstIdx.wget[1]
Blocking rules: (none)
Rule: res_inSndHalf_processEnq
Predicate: res_inSndHalf_finishInit &&
res_inSndHalf_enqIdx.whas && res_inSndHalf_enqIdx.wget[1]
Blocking rules: (none)
Rule: res_inSndHalf_updateFreeReg
Predicate: res_inSndHalf_finishInit &&
((res_inSndHalf_decrFreeIdx.whas &&
res_inSndHalf_decrFreeIdx.wget[1]) ||
(res_inSndHalf_deqIdx.whas && res_inSndHalf_deqIdx.wget[1]))
Blocking rules: (none)
Rule: res_inSndHalf_updateUsedReg
Predicate: res_inSndHalf_finishInit &&
((res_inSndHalf_enqIdx.whas && res_inSndHalf_enqIdx.wget[1]) ||
(res_inSndHalf_deqIdx.whas && res_inSndHalf_deqIdx.wget[1]))
Blocking rules: (none)
Rule: res_inSndHalf_initialization
Predicate: ! res_inSndHalf_finishInit
Blocking rules: (none)
Rule: res_inFstHalf_processDeq
Predicate: res_inFstHalf_finishInit &&
res_inFstHalf_deqIdx.whas && res_inFstHalf_deqIdx.wget[1]
Blocking rules: (none)
Rule: res_inFstHalf_processFirstReq
Predicate: res_inFstHalf_finishInit &&
res_inFstHalf_firstIdx.whas && res_inFstHalf_firstIdx.wget[1]
Blocking rules: (none)
Rule: res_inFstHalf_processEnq
Predicate: res_inFstHalf_finishInit &&
res_inFstHalf_enqIdx.whas && res_inFstHalf_enqIdx.wget[1]
Blocking rules: (none)
Rule: res_inFstHalf_updateFreeReg
Predicate: res_inFstHalf_finishInit &&
((res_inFstHalf_decrFreeIdx.whas &&
res_inFstHalf_decrFreeIdx.wget[1]) ||
(res_inFstHalf_deqIdx.whas && res_inFstHalf_deqIdx.wget[1]))
Blocking rules: (none)
Rule: res_inFstHalf_updateUsedReg
Predicate: res_inFstHalf_finishInit &&
((res_inFstHalf_enqIdx.whas && res_inFstHalf_enqIdx.wget[1]) ||
(res_inFstHalf_deqIdx.whas && res_inFstHalf_deqIdx.wget[1]))
Blocking rules: (none)
Rule: res_inFstHalf_initialization
Predicate: ! res_inFstHalf_finishInit
Blocking rules: (none)
Logical execution order: outStream_putTokInfo,
inStream_putRecord,
inStream_putDeqTok,
inStream_getTokInfo,
res_feedScheduler,
res_nextToProcess,
outStream_getDeqTok_snd,
outStream_getDeqTok_fst,
res_compares,
outStream_getRecord_snd,
outStream_getRecord_fst,
res_inSndHalf_processFirstReq,
res_inSndHalf_processDeq,
res_inSndHalf_updateFreeReg,
res_inSndHalf_updateUsedReg,
res_inSndHalf_processEnq,
res_inFstHalf_processFirstReq,
res_inSndHalf_initialization,
res_inFstHalf_processDeq,
res_inFstHalf_updateFreeReg,
res_inFstHalf_updateUsedReg,
res_inFstHalf_processEnq,
res_inFstHalf_initialization
==========================================================
1.1 cryptosorter/memocodeDesignContest2008/sort/mkBRAMLevel3MergerInstance.sched
http://www.opencores.org/cvsweb.shtml/cryptosorter/memocodeDesignContest2008/sort/mkBRAMLevel3MergerInstance.sched?rev=1.1&content-type=text/x-cvsweb-markup
Index: mkBRAMLevel3MergerInstance.sched
===================================================================
=== Generated schedule for mkBRAMLevel3MergerInstance ===
Method schedule
---------------
Method: inStream_getTokInfo
Ready signal: res_inFstHalf_finishInit && res_inSndHalf_finishInit
Conflict-free: inStream_getTokInfo,
inStream_putDeqTok,
inStream_putRecord,
outStream_putTokInfo,
outStream_getDeqTok_fst,
outStream_getDeqTok_snd,
outStream_getRecord_fst,
outStream_getRecord_snd
Method: inStream_putDeqTok
Ready signal: res_inSndHalf_finishInit && res_inFstHalf_finishInit
Conflict-free: inStream_getTokInfo,
inStream_putRecord,
outStream_putTokInfo,
outStream_getDeqTok_fst,
outStream_getDeqTok_snd,
outStream_getRecord_fst,
outStream_getRecord_snd
Conflicts: inStream_putDeqTok
Method: inStream_putRecord
Ready signal: res_inSndHalf_finishInit && res_inFstHalf_finishInit
Conflict-free: inStream_getTokInfo,
inStream_putDeqTok,
outStream_putTokInfo,
outStream_getDeqTok_fst,
outStream_getDeqTok_snd,
outStream_getRecord_fst,
outStream_getRecord_snd
Conflicts: inStream_putRecord
Method: outStream_putTokInfo
Ready signal: True
Conflict-free: inStream_getTokInfo,
inStream_putDeqTok,
inStream_putRecord,
outStream_getRecord_fst,
outStream_getRecord_snd
Sequenced before (restricted): outStream_getDeqTok_fst,
outStream_getDeqTok_snd
Conflicts: outStream_putTokInfo
Method: outStream_getDeqTok_fst
Ready signal: res_getDeqTokW.whas && res_getDeqTokW.wget[2]
Conflict-free: inStream_getTokInfo,
inStream_putDeqTok,
inStream_putRecord,
outStream_getDeqTok_fst,
outStream_getDeqTok_snd,
outStream_getRecord_fst,
outStream_getRecord_snd
Sequenced after (restricted): outStream_putTokInfo
Method: outStream_getDeqTok_snd
Ready signal: res_getDeqTokW.whas && res_getDeqTokW.wget[2]
Conflict-free: inStream_getTokInfo,
inStream_putDeqTok,
inStream_putRecord,
outStream_getDeqTok_fst,
outStream_getDeqTok_snd,
outStream_getRecord_fst,
outStream_getRecord_snd
Sequenced after (restricted): outStream_putTokInfo
Method: outStream_getRecord_fst
Ready signal: res_outW.whas && res_outW.wget[131]
Conflict-free: inStream_getTokInfo,
inStream_putDeqTok,
inStream_putRecord,
outStream_putTokInfo,
outStream_getDeqTok_fst,
outStream_getDeqTok_snd,
outStream_getRecord_fst,
outStream_getRecord_snd
Method: outStream_getRecord_snd
Ready signal: res_outW.whas && res_outW.wget[131]
Conflict-free: inStream_getTokInfo,
inStream_putDeqTok,
inStream_putRecord,
outStream_putTokInfo,
outStream_getDeqTok_fst,
outStream_getDeqTok_snd,
outStream_getRecord_fst,
outStream_getRecord_snd
Rule schedule
-------------
Rule: res_compares
Predicate: res_inFstHalf_ugbram_bram.RDY_read_resp &&
res_inSndHalf_ugbram_bram.RDY_read_resp &&
res_inFstHalf_finishInit &&
res_inSndHalf_finishInit && res_reqQ.i_notEmpty
Blocking rules: (none)
Rule: res_nextToProcess
Predicate: res_inFstHalf_finishInit &&
res_inSndHalf_finishInit &&
((! res_scheduler_getNextW.whas) ||
(! res_scheduler_getNextW.wget[2]) ||
res_reqQ.i_notFull)
Blocking rules: (none)
Rule: res_feedScheduler
Predicate: (((res_nextTokW.whas
? res_nextTokW.wget[2:0]
: _) ==
3'd0) ||
res_inFstHalf_finishInit) &&
(((res_nextTokW.whas
? res_nextTokW.wget[2:0]
: _) ==
3'd0) ||
(((res_scheduler_last[2]
? res_scheduler_last[1:0]
: _) ==
2 |
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