Message

Reply | Reply all

Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

From: cvs at opencores.org<cvs@o...>
Date: Sat May 24 17:29:11 CEST 2008
Subject: [cvs-checkins] MODIFIED: z80soc ...
Date: 00/08/05 24:17:29

Modified: z80soc/DE1/rtl/VHDL vram8k.vhd
Log:
Version 0.6


Revision Changes Path
1.2 z80soc/DE1/rtl/VHDL/vram8k.vhd

http://www.opencores.org/cvsweb.shtml/z80soc/DE1/rtl/VHDL/vram8k.vhd.diff?r1=1.1&r2=1.2

(In the diff below, changes in quantity of whitespace are not shown.)

Index: vram8k.vhd
===================================================================
RCS file: /cvsroot/rrred/z80soc/DE1/rtl/VHDL/vram8k.vhd,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- vram8k.vhd 4 May 2008 20:53:37 -0000 1.1
+++ vram8k.vhd 24 May 2008 15:29:11 -0000 1.2
@@ -42,14 +42,16 @@
ENTITY vram8k IS
PORT
(
- data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
- rdaddress : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
- rdclock : IN STD_LOGIC ;
- rden : IN STD_LOGIC := '1';
- wraddress : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
- wrclock : IN STD_LOGIC ;
- wren : IN STD_LOGIC := '1';
- q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+ address_a : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
+ address_b : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
+ clock_a : IN STD_LOGIC ;
+ clock_b : IN STD_LOGIC ;
+ data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ wren_a : IN STD_LOGIC := '1';
+ wren_b : IN STD_LOGIC := '1';
+ q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+ q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END vram8k;

@@ -57,6 +59,7 @@
ARCHITECTURE SYN OF vram8k IS

SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
+ SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0);



@@ -67,35 +70,43 @@
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
+ indata_reg_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
+ outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
+ outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
- rdcontrol_reg_b : STRING;
+ read_during_write_mode_mixed_ports : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
- width_byteena_a : NATURAL
+ width_byteena_a : NATURAL;
+ width_byteena_b : NATURAL;
+ wrcontrol_wraddress_reg_b : STRING
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
+ wren_b : IN STD_LOGIC ;
clock1 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
- rden_b : IN STD_LOGIC ;
+ q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
- data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0)
+ data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;

BEGIN
- q <= sub_wire0(7 DOWNTO 0);
+ q_a <= sub_wire0(7 DOWNTO 0);
+ q_b <= sub_wire1(7 DOWNTO 0);

altsyncram_component : altsyncram GENERIC MAP ( @@ -104,30 +115,37 @@ clock_enable_input_b => "BYPASS", clock_enable_output_a => "BYPASS", clock_enable_output_b => "BYPASS", + indata_reg_b => "CLOCK1", intended_device_family => "Cyclone II", lpm_type => "altsyncram", numwords_a => 8192, numwords_b => 8192, - operation_mode => "DUAL_PORT", + operation_mode => "BIDIR_DUAL_PORT", + outdata_aclr_a => "NONE", outdata_aclr_b => "NONE", + outdata_reg_a => "UNREGISTERED", outdata_reg_b => "UNREGISTERED", power_up_uninitialized => "FALSE", - rdcontrol_reg_b => "CLOCK1", + read_during_write_mode_mixed_ports => "OLD_DATA", widthad_a => 13, widthad_b => 13, width_a => 8, width_b => 8, - width_byteena_a => 1 + width_byteena_a => 1, + width_byteena_b => 1, + wrcontrol_wraddress_reg_b => "CLOCK1" ) PORT MAP ( - wren_a => wren, - clock0 => wrclock, - clock1 => rdclock, - address_a => wraddress, - address_b => rdaddress, - rden_b => rden, - data_a => data, - q_b => sub_wire0 + wren_a => wren_a, + clock0 => clock_a, + wren_b => wren_b, + clock1 => clock_b, + address_a => address_a, + address_b => address_b, + data_a => data_a, + data_b => data_b, + q_a => sub_wire0, + q_b => sub_wire1 ); @@ -155,14 +173,14 @@ -- Retrieval info: PRIVATE: CLRrren NUMERIC "0" -- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" -- Retrieval info: PRIVATE: CLRwren NUMERIC "0" --- Retrieval info: PRIVATE: Clock NUMERIC "1" +-- Retrieval info: PRIVATE: Clock NUMERIC "5" -- Retrieval info: PRIVATE: Clock_A NUMERIC "0" -- Retrieval info: PRIVATE: Clock_B NUMERIC "0" -- Retrieval info: PRIVATE: ECC NUMERIC "0" -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" -- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" --- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0" --- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B" +-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1" +-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" @@ -171,17 +189,17 @@ -- Retrieval info: PRIVATE: MEMSIZE NUMERIC "65536" -- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" -- Retrieval info: PRIVATE: MIFfilename STRING "" --- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2" +-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" -- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" -- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" --- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "1" -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" -- Retrieval info: PRIVATE: REGdata NUMERIC "1" --- Retrieval info: PRIVATE: REGq NUMERIC "1" --- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1" --- Retrieval info: PRIVATE: REGrren NUMERIC "1" +-- Retrieval info: PRIVATE: REGq NUMERIC "0" +-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0" +-- Retrieval info: PRIVATE: REGrren NUMERIC "0" -- Retrieval info: PRIVATE: REGwraddress NUMERIC "1" -- Retrieval info: PRIVATE: REGwren NUMERIC "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" @@ -193,50 +211,59 @@ -- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8" -- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8" -- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" --- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0" +-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1" -- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" -- Retrieval info: PRIVATE: enable NUMERIC "0" --- Retrieval info: PRIVATE: rden NUMERIC "1" +-- Retrieval info: PRIVATE: rden NUMERIC "0" -- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1" -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" +-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192" -- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "8192" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" +-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" -- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" +-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" -- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" -- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" --- Retrieval info: CONSTANT: RDCONTROL_REG_B STRING "CLOCK1" +-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "OLD_DATA" -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13" -- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "13" -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" -- Retrieval info: CONSTANT: WIDTH_B NUMERIC "8" -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" --- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0] --- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0] --- Retrieval info: USED_PORT: rdaddress 0 0 13 0 INPUT NODEFVAL rdaddress[12..0] --- Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL rdclock --- Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC rden --- Retrieval info: USED_PORT: wraddress 0 0 13 0 INPUT NODEFVAL wraddress[12..0] --- Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT NODEFVAL wrclock --- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren --- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 --- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 --- Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0 --- Retrieval info: CONNECT: @address_a 0 0 13 0 wraddress 0 0 13 0 --- Retrieval info: CONNECT: @address_b 0 0 13 0 rdaddress 0 0 13 0 --- Retrieval info: CONNECT: @rden_b 0 0 0 0 rden 0 0 0 0 --- Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0 --- Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0 +-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1" +-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1" +-- Retrieval info: USED_PORT: address_a 0 0 13 0 INPUT NODEFVAL address_a[12..0] +-- Retrieval info: USED_PORT: address_b 0 0 13 0 INPUT NODEFVAL address_b[12..0] +-- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT NODEFVAL clock_a +-- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL clock_b +-- Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL data_a[7..0] +-- Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL data_b[7..0] +-- Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL q_a[7..0] +-- Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL q_b[7..0] +-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a +-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b +-- Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0 +-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0 +-- Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0 +-- Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0 +-- Retrieval info: CONNECT: @address_a 0 0 13 0 address_a 0 0 13 0 +-- Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0 +-- Retrieval info: CONNECT: @address_b 0 0 13 0 address_b 0 0 13 0 +-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0 +-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0 +-- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: GEN_FILE: TYPE_NORMAL vram8k.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL vram8k.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL vram8k.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL vram8k.bsf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL vram8k.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL vram8k_inst.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL vram8k_waveforms.html TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL vram8k_wave*.jpg FALSE