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From: cvs at opencores.org<cvs@o...>
Date: Wed May 21 16:37:15 CEST 2008
Subject: [cvs-checkins] MODIFIED: m1_core ...
Date: 00/08/05 21:16:37

Modified: m1_core/hdl/rtl/m1_cpu m1_cpu.v
Log:
Corrected some bugs found by Simone Lunardo and Paolo Piscopo.




Revision Changes Path
1.3 m1_core/hdl/rtl/m1_cpu/m1_cpu.v

http://www.opencores.org/cvsweb.shtml/m1_core/hdl/rtl/m1_cpu/m1_cpu.v.diff?r1=1.2&r2=1.3

(In the diff below, changes in quantity of whitespace are not shown.)

Index: m1_cpu.v
===================================================================
RCS file: /cvsroot/fafa1971/m1_core/hdl/rtl/m1_cpu/m1_cpu.v,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -b -r1.2 -r1.3
--- m1_cpu.v 18 Feb 2008 12:38:07 -0000 1.2
+++ m1_cpu.v 21 May 2008 14:37:14 -0000 1.3
@@ -233,7 +233,7 @@
// Wires connected to the Divider module instance
wire[31:0] div_a_i = id_ex_alu_a;
wire[31:0] div_b_i = id_ex_alu_b;
- wire div_signed_i;
+ wire div_signed_i = id_ex_alu_signed;
wire[31:0] div_quotient_o;
wire[31:0] div_remainder_o;
reg div_req_i; // Alternating Bit Protocol (ABP) request must be stored
@@ -288,8 +288,8 @@
SysCon[24] <= 0; SysCon[25] <= 0; SysCon[26] <= 0; SysCon[27] <= 0; SysCon[28] <= 0; SysCon[29] <= 0; SysCon[30] <= 0; SysCon[31] <= 0;

// Initialize ABP requests to instantiated modules
- mul_req_i <= 0;
- div_req_i <= 0;
+ mul_req_i = 0;
+ div_req_i = 0;

// Latch 1: IF/ID
if_id_opcode <= `NOP;
@@ -1907,6 +1907,10 @@
end else begin

$display("INFO: CPU(%m)-MEM: Propagating value %X", ex_mem_aluout);
+ if(ex_mem_desthi) begin // Swap halves
+ mem_wb_value[63:32] <= ex_mem_aluout[31:0];
+ mem_wb_value[31:0] <= ex_mem_aluout[63:32];
+ end else // Default case
mem_wb_value <= ex_mem_aluout;

end