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From: cvs at opencores.org<cvs@o...>
Date: Thu May 15 21:57:02 CEST 2008
Subject: [cvs-checkins] MODIFIED: spi_slave ...
Date: 00/08/05 15:21:57

Modified: spi_slave/bench/vhdl opb_spi_slave_tb.vhd
Log:
changed test TX-CRC Block from end of block to start

change crc value eb99fa90 to e4ea78bf


Revision Changes Path
1.4 spi_slave/bench/vhdl/opb_spi_slave_tb.vhd

http://www.opencores.org/cvsweb.shtml/spi_slave/bench/vhdl/opb_spi_slave_tb.vhd.diff?r1=1.3&r2=1.4

(In the diff below, changes in quantity of whitespace are not shown.)

Index: opb_spi_slave_tb.vhd
===================================================================
RCS file: /cvsroot/dkoethe/spi_slave/bench/vhdl/opb_spi_slave_tb.vhd,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -b -r1.3 -r1.4
--- opb_spi_slave_tb.vhd 24 Mar 2008 19:41:07 -0000 1.3
+++ opb_spi_slave_tb.vhd 15 May 2008 19:57:02 -0000 1.4
@@ -6,7 +6,7 @@
-- Author :
-- Company :
-- Created : 2007-09-02
--- Last update: 2008-03-23
+-- Last update: 2008-05-15
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
@@ -248,7 +248,7 @@
if (OPB_Transfer_Abort) then
MOPB_errAck <= '1';
else
- if (conv_integer(M_ABus)>=16#24000000#) then
+ if (conv_integer(M_ABus) >= 16#24000000#) then
if (M_RNW = '1') then
-- read
OPB_DBus0(C_OPB_DWIDTH-C_SR_WIDTH to C_OPB_DWIDTH-1) <= "0000000000000000" & "00" & M_ABus(16 to C_OPB_DWIDTH-3);
@@ -756,19 +756,19 @@
end loop; -- i

-- crc_block
- for i in 16 to 30 loop
+ for i in 16 to 31 loop
spi_transfer(conv_std_logic_vector(i, C_SR_WIDTH));
+ if (i = 16) then
+ assert (conv_integer(spi_value_in) = 16#e4ea78bf#) report "DMA-block CRC failure" severity failure;
+ else
assert (conv_integer(spi_value_in) = i) report "DMA Transfer 1 read data failure" severity failure;
+ end if;
end loop; -- i

- -- check CRC
- spi_transfer(conv_std_logic_vector(31, C_SR_WIDTH));
- assert (conv_integer(spi_value_in) = 16#eb99fa90#) report "TX CRC_Failure" severity failure;
-
-- wait until RX transfer done
for i in 0 to 15 loop
opb_read(C_ADR_STATUS);
- if (opb_read_data(SPI_SR_Bit_RX_DMA_Done) ='1') then
+ if (opb_read_data(SPI_SR_Bit_RX_DMA_Done) = '1') then
exit;
end if;
wait for 1 us;
@@ -776,11 +776,11 @@

-- check TX CRC Register
opb_read(C_ADR_TX_CRC);
- assert (conv_integer(opb_read_data)=16#eb99fa90#) report "TX Register CRC Failure" severity failure;
+ assert (conv_integer(opb_read_data) = 16#e4ea78bf#) report "TX Register CRC Failure" severity failure;

-- check RX CRC Register
opb_read(C_ADR_RX_CRC);
- assert (conv_integer(opb_read_data)=16#eb99fa90#) report "RX Register CRC Failure" severity failure;
+ assert (conv_integer(opb_read_data) = 16#e4ea78bf#) report "RX Register CRC Failure" severity failure;

wait for 1 us;
end if;