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From: cvs at opencores.org<cvs@o...>
Date: Thu May 15 21:55:08 CEST 2008
Subject: [cvs-checkins] MODIFIED: spi_slave ...
Date: 00/08/05 15:21:55

Modified: spi_slave/pcore/opb_spi_slave_v1_00_a/hdl/vhdl crc_core.vhd
Log:
moved TX CRC Value from end of packet to the start.


Revision Changes Path
1.3 spi_slave/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/crc_core.vhd

http://www.opencores.org/cvsweb.shtml/spi_slave/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/crc_core.vhd.diff?r1=1.2&r2=1.3

(In the diff below, changes in quantity of whitespace are not shown.)

Index: crc_core.vhd
===================================================================
RCS file: /cvsroot/dkoethe/spi_slave/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/crc_core.vhd,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -b -r1.2 -r1.3
--- crc_core.vhd 15 May 2008 18:16:41 -0000 1.2
+++ crc_core.vhd 15 May 2008 19:55:08 -0000 1.3
@@ -41,8 +41,10 @@
signal tx_crc_en : std_logic;


- signal cnt : integer range 0 to 15;
-
+ type state_define is (idle,
+ tx_insert_crc,
+ wait_done);
+ signal state : state_define;

begin -- behavior

@@ -83,20 +85,43 @@
begin
if (rst = '1') then
tx_crc_insert <= '0';
+ state <= idle;
elsif rising_edge(OPB_Clk) then
+ case state is
+ when idle =>
+ if (opb_m_last_block = '1') then
+ tx_crc_insert <= '1';
+ state <= tx_insert_crc;
+ else
+ tx_crc_insert <= '0';
+ state <= idle;
+ end if;
+
+ when tx_insert_crc =>
if (opb_m_last_block = '0') then
- cnt <= 15;
+ -- abort
tx_crc_insert <= '0';
+ state <= idle;
elsif (fifo_tx_en = '1') then
- if (cnt = 1) then
- tx_crc_insert <= '1';
- cnt <= cnt -1;
- elsif (cnt = 0) then
tx_crc_insert <= '0';
+ state <= wait_done;
else
- cnt <= cnt -1;
+ state <= tx_insert_crc;
end if;
+
+ when wait_done =>
+ if (opb_m_last_block = '0') then
+ tx_crc_insert <= '0';
+ state <= idle;
+
+ else
+ state <= wait_done;
end if;
+
+ when others =>
+ state <= idle;
+ end case;
+
end if;
end process;
end behavior;