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From: cvs at opencores.org<cvs@o...>
Date: Tue Apr 29 23:16:07 CEST 2008
Subject: [cvs-checkins] MODIFIED: t48 ...
Date: 00/08/04 29:23:16

Modified: t48/syn/t8048/b5x300 compile_list gen_ise_project.tcl
Log:
update to new mnemonic decoder






Revision Changes Path
1.2 t48/syn/t8048/b5x300/compile_list

http://www.opencores.org/cvsweb.shtml/t48/syn/t8048/b5x300/compile_list.diff?r1=1.1&r2=1.2

(In the diff below, changes in quantity of whitespace are not shown.)

Index: compile_list
===================================================================
RCS file: /cvsroot/arniml/t48/syn/t8048/b5x300/compile_list,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- compile_list 12 Apr 2008 21:27:07 -0000 1.1
+++ compile_list 29 Apr 2008 21:16:07 -0000 1.2
@@ -8,11 +8,9 @@
../../../rtl/vhdl/dmem_ctrl_pack-p.vhd
../../../rtl/vhdl/dmem_ctrl.vhd
../../../rtl/vhdl/decoder_pack-p.vhd
-../../../rtl/vhdl/opc_table.vhd
../../../rtl/vhdl/cond_branch_pack-p.vhd
../../../rtl/vhdl/alu_pack-p.vhd
../../../rtl/vhdl/t48_comp_pack-p.vhd
-../../../rtl/vhdl/opc_decoder.vhd
../../../rtl/vhdl/int.vhd
../../../rtl/vhdl/t48_tb_pack-p.vhd
../../../rtl/vhdl/decoder.vhd



1.2 t48/syn/t8048/b5x300/gen_ise_project.tcl

http://www.opencores.org/cvsweb.shtml/t48/syn/t8048/b5x300/gen_ise_project.tcl.diff?r1=1.1&r2=1.2

(In the diff below, changes in quantity of whitespace are not shown.)

Index: gen_ise_project.tcl
===================================================================
RCS file: /cvsroot/arniml/t48/syn/t8048/b5x300/gen_ise_project.tcl,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- gen_ise_project.tcl 12 Apr 2008 21:27:07 -0000 1.1
+++ gen_ise_project.tcl 29 Apr 2008 21:16:07 -0000 1.2
@@ -1,6 +1,6 @@
###############################################################################
#
-# $Id: gen_ise_project.tcl,v 1.1 2008/04/12 21:27:07 arniml Exp $
+# $Id: gen_ise_project.tcl,v 1.2 2008/04/29 21:16:07 arniml Exp $
#
# Based on
# Created by Phil Hays, Xilinx
@@ -148,12 +148,14 @@

project set {Optimization Goal} Area -process {Synthesize - XST}
project set {Optimization Effort} Normal -process {Synthesize - XST}
+project set {Use Synthesis Constraints File} 1 -process {Synthesize - XST}
+
#project set "Map Effort Level" High
#project set {Perform Timing-Driven Packing and Placement} 1
project set {Place & Route Effort Level (Overall)} Standard
#project set "Other Place & Route Command Line Options" "-intsyle xflow"
project set {Generate Post-Place & Route Static Timing Report} true
-project set {Report Uncovered Paths} 10 -process {Generate Post-Place & Route Static Timing}
+project set {Report Unconstrained Paths} 10 -process {Generate Post-Place & Route Static Timing}
project set {Report Type} {Verbose Report} -process {Generate Post-Place & Route Static Timing}
project set {Create Binary Configuration File} 1 -process {Generate Programming File}